Leakage power minimization in deep sub-micron technology by exploiting positive slacks of dependent paths

Leakage power minimization is one of the key aspects of modern multi-million low power system-on-chip (SoC) design. In post timing-closure phase, leakage-in-place-optimization (LIPO) is generally adopted to reduce leakage power by swapping high-leaky cells in the timing-data-paths by low-leaky ones of the same footprint. The traditional LIPO does not touch the clock network for leakage recovery. This paper investigates the opportunity to reduce leakage power further of an already leakage-power-minimized (by LIPO), timing closed design by minimally altering the balanced clock tree. The proposed method, Opportunistic LIPO, intends to borrow unused positive-slack from downstream (and/or upstream) paths, may or may not be at immediate neighborhood, and provide a “positive skew” (and/or “negative skew”) at the capture (and/or launch) clock edge of the current path. In this way, the proposed scheme creates an opportunity in the current path to increase the low-leaky cells distribution. Experimental results, computed over some practical duration (less than 48 hours), on some industry-standard design based on 28nm technology, of having around 50 million gates, shows that the proposed algorithm, “Opportunistic LIPO”, achieves 10-30% better leakage power as compared to traditional LIPO without increasing the number of timing violations and having no significant impact on overall area.