2016 International Great Lakes Symposium on VLSI (GLSVLSI)最新文献_第5页

Exploring configurable non-volatile memory-based caches for energy-efficient embedded systems 探索用于节能嵌入式系统的可配置非易失性存储器缓存

2016 International Great Lakes Symposium on VLSI (GLSVLSI) Pub Date : 2016-05-18 DOI: 10.1145/2902961.2903009

Tosiron Adegbija

引用次数: 3

Graphene-PLA (GPLA): A compact and ultra-low power logic array architecture 石墨烯-聚乳酸(GPLA):一种紧凑的超低功耗逻辑阵列架构

2016 International Great Lakes Symposium on VLSI (GLSVLSI) Pub Date : 2016-05-18 DOI: 10.1145/2902961.2902970

V. Tenace, A. Calimera, E. Macii, M. Poncino

引用次数: 5

Design of error-resilient logic gates with reinforcement using implications 基于隐含强化的容错逻辑门设计

2016 International Great Lakes Symposium on VLSI (GLSVLSI) Pub Date : 2016-05-18 DOI: 10.1145/2902961.2902983

Xijing Han, M. Donato, R. I. Bahar, A. Zaslavsky, W. Patterson

引用次数: 5

The applications of NVM technology in hardware security NVM技术在硬件安全中的应用

2016 International Great Lakes Symposium on VLSI (GLSVLSI) Pub Date : 2016-05-18 DOI: 10.1145/2902961.2903043

Chaofei Yang, Beiye Liu, Yandan Wang, Yiran Chen, Hai Helen Li, Xian Zhang, Guangyu Sun

引用次数: 10

FCM: Towards fine-grained GPU power management for closed source mobile games FCM:面向闭源手机游戏的细粒度GPU电源管理

2016 International Great Lakes Symposium on VLSI (GLSVLSI) Pub Date : 2016-05-18 DOI: 10.1145/2902961.2902989

Jiachen Song, Xi Li, Beilei Sun, Zhinan Cheng, Chao Wang, Xuehai Zhou

引用次数: 9

Red-shield: Shielding read disturbance for STT-RAM based register files on GPUs 红盾:屏蔽gpu上基于STT-RAM的寄存器文件的读取干扰

2016 International Great Lakes Symposium on VLSI (GLSVLSI) Pub Date : 2016-05-18 DOI: 10.1145/2902961.2902988

Hang Zhang, Xuhao Chen, Nong Xiao, Fang Liu, Zhiguang Chen

{"title":"Red-shield: Shielding read disturbance for STT-RAM based register files on GPUs","authors":"Hang Zhang, Xuhao Chen, Nong Xiao, Fang Liu, Zhiguang Chen","doi":"10.1145/2902961.2902988","DOIUrl":"https://doi.org/10.1145/2902961.2902988","url":null,"abstract":"To address the high energy consumption issue of SRAM on GPUs, emerging Spin-Transfer Torque (STT-RAM) memory technology has been intensively studied to build GPU register files for better energy-efficiency, thanks to its benefits of low leakage power, high density, and good scalability. However, STT-RAM suffers from a reliability issue, read disturbance, which stems from the fact that the voltage difference between read current and write current becomes smaller as technology scales. The read disturbance leads to high error rates for read operations, which cannot be effectively protected by SECDEC ECC on large-capacity register files of GPUs. Prior schemes (e.g. read-restore) to mitigate the read disturbance usually incur either non-trivial performance loss or excessive energy overhead, thus not applicable for the GPU register file design which aims to achieve both high performance and energy-efficiency. To combat the read disturbance on GPU register files, we propose a novel software-hardware co-designed solution, i.e. Red-Shield, which consists of three optimizations to overcome limitations of the existing solutions. First, we identify dead reads at compiling stage and augment instructions to avoid unnecessary restores. Second, we employ a small read buffer to accommodate register reads with high access locality to further reduce restores. Third, we propose an adaptive restore mechanism to selectively pick the suitable restore scheme, according to the busy status of corresponding register banks. Experimental results show that our proposed design can effectively mitigate the performance loss and energy overhead caused by restore operations, while still maintaining the reliability of reads.","PeriodicalId":407054,"journal":{"name":"2016 International Great Lakes Symposium on VLSI (GLSVLSI)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128754188","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

Reduced overhead gate level logic encryption 减少开销门级逻辑加密

2016 International Great Lakes Symposium on VLSI (GLSVLSI) Pub Date : 2016-05-18 DOI: 10.1145/2902961.2902972

Kyle Juretus, I. Savidis

引用次数: 25

Real-time hardware stereo matching using guided image filter 基于引导图像滤波的实时硬件立体匹配

2016 International Great Lakes Symposium on VLSI (GLSVLSI) Pub Date : 2016-05-18 DOI: 10.1145/2902961.2902995

Chen-Yu Yang, Yan Li, Wei Zhong, Song Chen

引用次数: 8

Exploring main memory design based on racetrack memory technology 探索基于赛马场存储技术的主存储器设计

2016 International Great Lakes Symposium on VLSI (GLSVLSI) Pub Date : 2016-05-18 DOI: 10.1145/2902961.2902967

Qingda Hu, Guangyu Sun, J. Shu, Chao Zhang

{"title":"Exploring main memory design based on racetrack memory technology","authors":"Qingda Hu, Guangyu Sun, J. Shu, Chao Zhang","doi":"10.1145/2902961.2902967","DOIUrl":"https://doi.org/10.1145/2902961.2902967","url":null,"abstract":"Emerging non-volatile memories (NVMs), which include PC-RAM and STT-RAM, have been proposed to replace DRAM, mainly because they have better scalability and lower standby power. However, previous research has demonstrated that these NVMs cannot completely replace DRAM due to either lifetime/performance (PCRAM) or density (STT-RAM) issues. Recently, a new type of emerging NVM, called Racetrack Memory (RM), has attracted more and more attention of memory researchers because it has ultra-high density and fast access speed without the write cycle issue. However, there lacks research on how to leverage RM for main memory. To this end, we explore main memory design based on RM technology in both circuit and architecture levels. In the circuit level, we propose the structure of the RM based main memory and investigate different design parameters. In the architecture level, we design a simple and efficient shift-sense address mapping policy to reduce 95% shift operations for performance improvement and power saving. At the same time, we analyze the efficiency of existing optimization strategies for NVM main memory. Our experiments show that RM can outperform DRAM for main memory, in respect of density, performance, and energy efficiency.","PeriodicalId":407054,"journal":{"name":"2016 International Great Lakes Symposium on VLSI (GLSVLSI)","volume":"100 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117258787","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 24

Learning-based near-optimal area-power trade-offs in hardware design for neural signal acquisition 神经信号采集硬件设计中基于学习的近最优面积功率权衡

2016 International Great Lakes Symposium on VLSI (GLSVLSI) Pub Date : 2016-05-18 DOI: 10.1145/2902961.2903028

C. Aprile, Luca Baldassarre, Vipul Gupta, Juhwan Yoo, Mahsa Shoaran, Y. Leblebici, V. Cevher

引用次数: 4