2016 International Great Lakes Symposium on VLSI (GLSVLSI)最新文献_第4页

Reducing soft-error vulnerability of caches using data compression 利用数据压缩减少缓存的软错误漏洞

2016 International Great Lakes Symposium on VLSI (GLSVLSI) Pub Date : 2016-05-18 DOI: 10.1145/2902961.2902977

Sparsh Mittal, J. Vetter

引用次数: 11

A metastability immune timing error masking flip-flop for dynamic variation tolerance 一种亚稳态免疫时序误差掩蔽触发器，用于动态变化容忍

2016 International Great Lakes Symposium on VLSI (GLSVLSI) Pub Date : 2016-05-18 DOI: 10.1145/2902961.2902976

Govinda Sannena, B. P. Das

引用次数: 6

Defense systems and IoT: Security issues in an era of distributed command and control 国防系统和物联网:分布式指挥和控制时代的安全问题

2016 International Great Lakes Symposium on VLSI (GLSVLSI) Pub Date : 2016-05-18 DOI: 10.1145/2902961.2903038

Doug Palmer, Saverio Fazzari, S. Wartenberg

引用次数: 3

Temperature-aware dynamic voltage scaling for near-threshold computing 近阈值计算的温度感知动态电压缩放

2016 International Great Lakes Symposium on VLSI (GLSVLSI) Pub Date : 2016-05-18 DOI: 10.1145/2902961.2902997

S. Kiamehr, Mojtaba Ebrahimi, M. Tahoori

引用次数: 4

Concurrent error detection for reliable SHA-3 design 并发错误检测可靠的SHA-3设计

2016 International Great Lakes Symposium on VLSI (GLSVLSI) Pub Date : 2016-05-18 DOI: 10.1145/2902961.2902985

Pei Luo, Cheng Li, Yunsi Fei

引用次数: 13

Secret sharing and multi-user authentication: From visual cryptography to RRAM circuits 秘密共享和多用户认证:从视觉密码到随机存储器电路

2016 International Great Lakes Symposium on VLSI (GLSVLSI) Pub Date : 2016-05-18 DOI: 10.1145/2902961.2903039

Md Tanvir Arafin, G. Qu

{"title":"Secret sharing and multi-user authentication: From visual cryptography to RRAM circuits","authors":"Md Tanvir Arafin, G. Qu","doi":"10.1145/2902961.2903039","DOIUrl":"https://doi.org/10.1145/2902961.2903039","url":null,"abstract":"In this era of Internet of Things (IoT), connectivity exists everywhere, among everything (including people) at all times. Therefore, security, trust, and privacy become crucial to the design and implementation of IoT devices [12]. However, it is challenging to build security into IoT devices because most of them are constrained by extremely limited resources such as the battery, memory, and computation power etc. Inspired by the concept of visual cryptography [4] that requires the least amount of computation and a recent work on pure hardware-based single-user authentication [6], we present a novel solution to the secret sharing and multi-user authentication problem. Our solution is built on the observation that non-volatile resistive memories display nice monotonic and additive properties during resistive state transitions. We demonstrate how to design a hardware dependent multi-user authentication protocol using resistive random access memory (RRAM)-based hardware and provide the necessary circuits for the application. Finally, we simulate the proposed circuit to understand the nature of the operation and practical problems that these designs encounter during operation.","PeriodicalId":407054,"journal":{"name":"2016 International Great Lakes Symposium on VLSI (GLSVLSI)","volume":"90 4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122103315","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6

Real-time analysis for wormhole NoC: Revisited and revised 虫洞NoC的实时分析:重新审视和修订

2016 International Great Lakes Symposium on VLSI (GLSVLSI) Pub Date : 2016-05-18 DOI: 10.1145/2902961.2903023

Qin Xiong, Zhonghai Lu, Fei Wu, C. Xie

引用次数: 28

Trellis-search based dynamic multi-path connection allocation for TDM-NoCs 基于网格搜索的tdm - noc动态多路径连接分配

2016 International Great Lakes Symposium on VLSI (GLSVLSI) Pub Date : 2016-05-18 DOI: 10.1145/2902961.2902968

Yong Chen, E. Matús, G. Fettweis

引用次数: 12

Inter-tier crosstalk noise on power delivery networks for 3-D ICs with inductively-coupled interconnects 带电感耦合互连的三维集成电路供电网络的层间串扰噪声

2016 International Great Lakes Symposium on VLSI (GLSVLSI) Pub Date : 2016-05-18 DOI: 10.1145/2902961.2903020

I. Papistas, V. Pavlidis

{"title":"Inter-tier crosstalk noise on power delivery networks for 3-D ICs with inductively-coupled interconnects","authors":"I. Papistas, V. Pavlidis","doi":"10.1145/2902961.2903020","DOIUrl":"https://doi.org/10.1145/2902961.2903020","url":null,"abstract":"Inductive links have been proposed as an inter-tier interconnect solution for three-dimensional (3-D) integrated systems. Combined with signal multiplexing, inductive links achieve high communication bandwidth comparable to that of through silicon vias. However, being a wireless medium, electromagnetic coupling between the inductive link and nearby on-chip interconnects can cause voltage fluctuations affecting interconnect performance. Although the interference of interconnects on the operation of inductive links has been investigated, the inverse problem has yet to be explored. Consequently, this paper performs an investigation on the effect of electromagnetic coupling on different topologies of power delivery networks (PDNs) in the vicinity of on-chip inductors. Results indicate that the interdigitated PDN topology suffers from the induced noise due to the inductive links of the neighbouring tiers exhibiting a minimum aggregate noise of 131.3 mV. Alternatively, the paired topologies exhibit a superior noise behaviour, achieving a 39.4% and 35.4% decrease in noise level for paired type I and paired type II topologies, respectively, compared to the interdigitated topology.","PeriodicalId":407054,"journal":{"name":"2016 International Great Lakes Symposium on VLSI (GLSVLSI)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128179738","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Hardware-accelerated software library drivers generation for IP-centric SoC designs 以ip为中心的SoC设计的硬件加速软件库驱动程序生成

2016 International Great Lakes Symposium on VLSI (GLSVLSI) Pub Date : 2016-05-18 DOI: 10.1145/2902961.2903026

M. Jassi, Uzair Sharif, Daniel Mueller-Gritschneder, Ulf Schlichtmann

{"title":"Hardware-accelerated software library drivers generation for IP-centric SoC designs","authors":"M. Jassi, Uzair Sharif, Daniel Mueller-Gritschneder, Ulf Schlichtmann","doi":"10.1145/2902961.2903026","DOIUrl":"https://doi.org/10.1145/2902961.2903026","url":null,"abstract":"In recent years, the semiconductor industry has been witnessing an increasing reuse of hardware IPs for System-on-Chip (SoC) designs and embedded computing systems on FPGA platforms with hard-core processors. The IP-reuse comes with an increasing complexity at the hardware-software (HW-SW) interface. The efforts required to access the HW through the increasingly complex HW-SW interface diminishes the potential IP-reuse productivity gain. In our work, we are proposing hierarchical drivers for accessing IP-subsystems and its generation for enabling easier SW application adaptation to HW-changes and faster design space exploration (DSE) on a targeted HW-accelerated SW libraries. At the lowest level, closest to the HW, is the hardware abstraction layer (HAL), these are the platform-specific register-access drivers. At the next layer are the drivers to access the registers and bit-fields of each IP component of the IP-library. Next are the IP-subsystems drivers. At the top-layer, closest to the SW, is the simple scheduler with SW interface library that provides access functions to the SW application. The drivers generator uses the HW knowledge of IPs and IP-subsystems encoded in IP-XACT for generating the drivers for both operating system (OS) and non-OS based applications. For the OS-based applications, user-space drivers are generated, as well as device tree source (DTS) and drivers mapping in the kernel-space. In a case study, we have validated our methodology while performing DSE for a video processing application targeted to an IP-library, both as non-OS and with OS on Xilinx Zynq-based FPGA.","PeriodicalId":407054,"journal":{"name":"2016 International Great Lakes Symposium on VLSI (GLSVLSI)","volume":"140 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131673878","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1