2016 International Great Lakes Symposium on VLSI (GLSVLSI)最新文献_第3页

Why is it so hard to make secure chips? 为什么制造安全的芯片这么难?

2016 International Great Lakes Symposium on VLSI (GLSVLSI) Pub Date : 2016-05-18 DOI: 10.1145/2902961.2902962

M. Witteman

引用次数: 0

Low-power multi-port memory architecture based on Spin Orbit Torque magnetic devices 基于自旋轨道转矩磁器件的低功耗多端口存储器结构

2016 International Great Lakes Symposium on VLSI (GLSVLSI) Pub Date : 2016-05-18 DOI: 10.1145/2902961.2903022

R. Bishnoi, Fabian Oboril, M. Tahoori

{"title":"Low-power multi-port memory architecture based on Spin Orbit Torque magnetic devices","authors":"R. Bishnoi, Fabian Oboril, M. Tahoori","doi":"10.1145/2902961.2903022","DOIUrl":"https://doi.org/10.1145/2902961.2903022","url":null,"abstract":"Multi-port memories are widely used as shared memory, such as register files, in a microprocessor system, and its number of ports and capacities are significantly increasing with every product generation. However, with technology advancements, multi-port memories are facing severe challenges due to their bit-cell leakage and scalability, as well as reliability issues due to increase in design complexity. In this paper, we design a novel multi-port memory architecture in which we employ emerging Spin Orbit Torque (SOT) magnetic devices as a storing component because of its several beneficial attributes such as non-volatility, scalability, zero-leakage, almost infinite endurance, low access latency, low area and immunity to soft-errors. Moreover, due to separate read and write current paths in these devices, simultaneous read and write operations can be performed on the same cell while maintaining data integrity. In our proposed architecture, we have demonstrated that with this characteristic of SOT, the read-write contention can be resolved inherently at the device-level, which can simplify the overall multi-port design. Experimental results show that our proposed multi-port design has low access latency, and high energy efficiency with negligible area overhead.","PeriodicalId":407054,"journal":{"name":"2016 International Great Lakes Symposium on VLSI (GLSVLSI)","volume":"224 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123385418","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 11

Neural network-based prediction algorithms for in-door multi-source energy harvesting system for non-volatile processors 基于神经网络的非易失性处理器室内多源能量收集系统预测算法

2016 International Great Lakes Symposium on VLSI (GLSVLSI) Pub Date : 2016-05-18 DOI: 10.1145/2902961.2903037

Ning Liu, Caiwen Ding, Yanzhi Wang, J. Hu

{"title":"Neural network-based prediction algorithms for in-door multi-source energy harvesting system for non-volatile processors","authors":"Ning Liu, Caiwen Ding, Yanzhi Wang, J. Hu","doi":"10.1145/2902961.2903037","DOIUrl":"https://doi.org/10.1145/2902961.2903037","url":null,"abstract":"Due to size, longevity, safety, and recharging concerns, energy harvesting is becoming a better choice for many wearable embedded systems than batteries. However, harvested energy is intrinsically unstable. In order to overcome this drawback, non-volatile processors (NVPs) have been proposed to bridge intermittent program execution. However, even with NVPs, frequent power interruptions will severely degrade system performance. Hence, in this paper we adopt a multi-source in-door energy harvesting architecture to compensate the shortcoming of single energy source. We further investigate power harvesting prediction techniques, which are critical for NVP systems since they can coordinate with task scheduler in the NVP system to compensate the intermittent ambient energy harvesting. We investigate prediction methods both for single energy harvesting source and for multiple energy harvesting sources, the total output power of which is more stable compared with the single source case. A comprehensive evaluation framework has been developed using actually measured harvesting traces on the proposed neural network-based power harvesting prediction methods. It turns out that the most favorable prediction methods are directly predicting the total output power of DC-DC converters (connecting between energy sources and NVP), or predicting the total input power of DC-DC converters first and then inferring the total output power using a learned mapping function, for multi-source power harvesting predictions.","PeriodicalId":407054,"journal":{"name":"2016 International Great Lakes Symposium on VLSI (GLSVLSI)","volume":"82 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121606134","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6

Quality of service-aware, scalable cache tuning algorithm in consumer-based embedded devices 基于消费者的嵌入式设备中服务感知质量、可扩展缓存调优算法

2016 International Great Lakes Symposium on VLSI (GLSVLSI) Pub Date : 2016-05-18 DOI: 10.1145/2902961.2902987

Mohamad Hammam Alsafrjalani, A. Gordon-Ross

引用次数: 6

8T1R: A novel low-power high-speed RRAM-based non-volatile SRAM design 8T1R:一种新型的低功耗高速非易失SRAM设计

2016 International Great Lakes Symposium on VLSI (GLSVLSI) Pub Date : 2016-05-18 DOI: 10.1145/2902961.2903016

A. Abdelwahed, A. Neale, M. Anis, Lan Wei

{"title":"8T1R: A novel low-power high-speed RRAM-based non-volatile SRAM design","authors":"A. Abdelwahed, A. Neale, M. Anis, Lan Wei","doi":"10.1145/2902961.2903016","DOIUrl":"https://doi.org/10.1145/2902961.2903016","url":null,"abstract":"With continuous and aggressive technology scaling, suppressing the stand-by power is among the top priorities for SRAM design. Switching off the less-frequently accessed blocks is an efficient way to reduce the stand-by power, provided that the information stored in these blocks can be restored. Non-volatile memories (NVMs) are integrated into SRAM cells to perform the required store and restore functions. Among various types of NVMs, memristors (a.k.a. RRAM) have several advantages including their small device size, low voltage operation, high speed, and CMOS-compatible fabrication process. In this article, we propose a new 8T1R RRAM-based non-volatile SRAM (NV-SRAM) which adds non-volatility to the SRAM with minimum impact on the Write and Read operations. Simulation at cell-level and array-level have confirmed that the new design performs Read and Write operations at a compatible delay, energy and noise margin as the conventional 6T SRAM, and it is among the best of all reported RRAM-based NV-SRAM designs to our knowledge. In addition, since our 8T1R design uses only one RRAM device per cell, the energy required for storing/restoring the SRAM data to/from the RRAM is significantly reduced by 60%/70% compared to the lowest storing/restoring energy of the previously proposed RRAM-based NV-SRAM designs.","PeriodicalId":407054,"journal":{"name":"2016 International Great Lakes Symposium on VLSI (GLSVLSI)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131617362","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 19

Load balanced on-chip power delivery for average current demand 负载平衡芯片上的电力输送平均电流需求

2016 International Great Lakes Symposium on VLSI (GLSVLSI) Pub Date : 2016-05-18 DOI: 10.1145/2902961.2903030

Divya Pathak, Mohammad Hossein Hajkazemi, Mohammad Khavari Tavana, H. Homayoun, I. Savidis

引用次数: 4

Tracking data flow at gate-level through structural 在门级通过结构跟踪数据流

2016 International Great Lakes Symposium on VLSI (GLSVLSI) Pub Date : 2016-05-18 DOI: 10.1145/2902961.2903040

Thao Le, J. Di, M. Tehranipoor, Domenic Forte, Lei Wang

引用次数: 9

A unified model of power sources for the simulation of electrical energy systems 用于电力系统仿真的统一电源模型

2016 International Great Lakes Symposium on VLSI (GLSVLSI) Pub Date : 2016-05-18 DOI: 10.1145/2902961.2903024

S. Vinco, Yukai Chen, E. Macii, M. Poncino

引用次数: 11

Low-power manycore accelerator for personalized biomedical applications 用于个性化生物医学应用的低功耗多核加速器

2016 International Great Lakes Symposium on VLSI (GLSVLSI) Pub Date : 2016-05-18 DOI: 10.1145/2902961.2902986

A. Page, Nasrin Attaran, Colin Shea, H. Homayoun, T. Mohsenin

{"title":"Low-power manycore accelerator for personalized biomedical applications","authors":"A. Page, Nasrin Attaran, Colin Shea, H. Homayoun, T. Mohsenin","doi":"10.1145/2902961.2902986","DOIUrl":"https://doi.org/10.1145/2902961.2902986","url":null,"abstract":"Wearable personal health monitoring systems can offer a cost effective solution for human healthcare. These systems must provide both highly accurate, secured and quick processing and delivery of vast amount of data. In addition, wearable biomedical devices are used in inpatient, outpatient, and at home e-Patient care that must constantly monitor the patient's biomedical and physiological signals 24/7. These biomedical applications require sampling and processing multiple streams of physiological signals with strict power and area footprint. The processing typically consists of feature extraction, data fusion, and classification stages that require a large number of digital signal processing and machine learning kernels. In response to these requirements, in this paper, a low-power, domain-specific manycore accelerator named Power Efficient Nano Clusters (PENC) is proposed to map and execute the kernels of these applications. Experimental results show that the manycore is able to reduce energy consumption by up to 80% and 14% for DSP and machine learning kernels, respectively, when optimally parallelized. The performance of the proposed PENC manycore when acting as a coprocessor to an Intel Atom processor is compared with existing commercial off-the-shelf embedded processing platforms including Intel Atom, Xilinx Artix-7 FPGA, and NVIDIA TK1 ARM-A15 with GPU SoC. The results show that the PENC manycore architecture reduces the energy by as much as 10X while outperforming all off-the-shelf embedded processing platforms across all studied machine learning classifiers.","PeriodicalId":407054,"journal":{"name":"2016 International Great Lakes Symposium on VLSI (GLSVLSI)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134481994","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 18

VarDroid: Online variability emulation in Android/Linux platforms VarDroid: Android/Linux平台上的在线可变性仿真

2016 International Great Lakes Symposium on VLSI (GLSVLSI) Pub Date : 2016-05-18 DOI: 10.1145/2902961.2902971

Pietro Mercati, Francesco Paterna, Andrea Bartolini, M. Imani, L. Benini, T. Simunic

引用次数: 1