{"title":"A necessary and sufficient condition for Lukasiewicz logic functions","authors":"N. Takagi, K. Nakashima, M. Mukaidono","doi":"10.1109/ISMVL.1996.508333","DOIUrl":"https://doi.org/10.1109/ISMVL.1996.508333","url":null,"abstract":"The literal, TSUM, min and max operations employed in multiple-valued logic design can be expressed in terms of the implication and the negation of Lukasiewicz logic. We can easily show that the set of multiple-valued functions composed of the above four operations and the negation is equivalent to the set of all multiple-valued functions composed of the Lukasiewicz implication and the negation. This implies that from the viewpoint of the multiple-valued logic design, Lukasiewicz multiple-valued logic is a fundamental system. In this paper, we clarify a necessary and sufficient condition for a multiple-valued function to be a Lukasiewicz logic function, which is defined as a function in terms of the Lukasiewicz implication and the negation.","PeriodicalId":403347,"journal":{"name":"Proceedings of 26th IEEE International Symposium on Multiple-Valued Logic (ISMVL'96)","volume":"233 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-01-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116397666","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"DT-an automated theorem prover for multiple-valued first-order predicate logics","authors":"S. Gerberding","doi":"10.1109/ISMVL.1996.508369","DOIUrl":"https://doi.org/10.1109/ISMVL.1996.508369","url":null,"abstract":"We describe the automated theorem prover \"Deep Thought\" (DT). The prover can be used for arbitrary multiple-valued first-order logics, provided the connectives can be defined by truth tables and the quantifiers are generalizations of the classical universal resp. existential quantifiers. DT has been tested with many interesting multiple-valued logics as well as classical first-order predicate logic. DT uses a free-variable semantic tableau calculus with generalized signs. For the existential tableau-rules two liberalized versions are implemented. The system utilizes a static index to control the application of axioms as wells as the search for applicable rules. A dynamic lemma generation strategy and various heuristics to control the tableau expansion and branch closure are integrated into DT. Theoretically, contradiction sets of arbitrary size can be discovered to close a branch.","PeriodicalId":403347,"journal":{"name":"Proceedings of 26th IEEE International Symposium on Multiple-Valued Logic (ISMVL'96)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-01-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126885678","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Alberto Bugarín-Diz, P. Cariñena, M. Delgado, S. Barro
{"title":"Petri net representation of fuzzy reasoning under incomplete information","authors":"Alberto Bugarín-Diz, P. Cariñena, M. Delgado, S. Barro","doi":"10.1109/ISMVL.1996.508356","DOIUrl":"https://doi.org/10.1109/ISMVL.1996.508356","url":null,"abstract":"In this paper we present an algorithm that performs reasoning processes on fuzzy knowledge bases with chaining between rules. The algorithm we propose permits obtaining valid inferences even in situations where part of the variables in the knowledge base are unknown. The support for the description of the execution algorithm is provided by the Petri net formalism, which organizes in a convenient way all the information in the base, and expresses in a simple way this and other processes performed onto it. This simplicity is mainly achieved also because the execution of the fuzzy knowledge base is carried out in a parameterized truth space using the linguistic truth values defined by J.F. Baldwin (1979), which reduces the computational cost of the process and makes easier its mapping onto the Petri net formalism.","PeriodicalId":403347,"journal":{"name":"Proceedings of 26th IEEE International Symposium on Multiple-Valued Logic (ISMVL'96)","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-01-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130856990","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Design of highly parallel linear digital circuits based on symbol-level redundancy","authors":"M. Nakajima, M. Kameyama","doi":"10.1109/ISMVL.1996.508344","DOIUrl":"https://doi.org/10.1109/ISMVL.1996.508344","url":null,"abstract":"In the non-linear digital system, it is difficult to design systematically highly parallel digital circuits whose output digit depends on a small number of input digits. On the other hand, the concept of linearity in digital systems is very attractive because analytical methods can be utilized to design highly parallel circuits. One of the most important problems in the design is to transform an original specification to a linear one. The design method of highly parallel circuits based on a necessary condition has been discussed. However, we cannot always find the solution even if the necessary condition is satisfied. To solve the problem, a sufficient condition for linearity is derived. If the sufficient condition is satisfied, we can design the linear circuit from the specification by the use of multiplicated redundant symbols.","PeriodicalId":403347,"journal":{"name":"Proceedings of 26th IEEE International Symposium on Multiple-Valued Logic (ISMVL'96)","volume":"125 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-01-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121743624","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Low-energy logic circuit techniques for multiple valued logic","authors":"K. Current, V. Oklobdzija, D. Maksimović","doi":"10.1109/ISMVL.1996.508341","DOIUrl":"https://doi.org/10.1109/ISMVL.1996.508341","url":null,"abstract":"Multiple valued logic (MVL) has been proposed as a means for reducing the power, improving the speed, and increasing the packing density of VLSI circuits. These performance improvements are achieved by designers who identify signal processing functions that can benefit from the design tradeoffs possible with MVL. Since advocates of MVL are accustomed to incorporating the possible tradeoffs of MVL techniques into specific VLSI design applications, these MVL designers may be able to take advantage of new energy saving circuit design techniques that may have tradeoffs that complement those of MVL. Low-energy (adiabatic) logic circuits have been proposed to reduce energy consumption of VLSI logic functions. Instead of the conventional dc power supply, these logic circuits use \"ac\" power supplies (power clocks) that allow energy recovery and also serve as timing clocks for the logic. It is possible to integrate all power switches and control circuitry on the chip with the low-energy logic. This results in better system efficiency and simpler power distribution. In this paper, concepts of adiabatic circuit design and the use of a high-frequency resonant power clock generator for adiabatic circuits will be summarized and then their possible application to low-energy, adiabatic multiple valued logic is discussed.","PeriodicalId":403347,"journal":{"name":"Proceedings of 26th IEEE International Symposium on Multiple-Valued Logic (ISMVL'96)","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-01-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121912060","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Logical not polynomial forms to represent multiple-valued functions","authors":"E. Zaitseva, T. Kalganova, E. Kochergov","doi":"10.1109/ISMVL.1996.508378","DOIUrl":"https://doi.org/10.1109/ISMVL.1996.508378","url":null,"abstract":"The synthesis of logical not polynomial forms to represent completely and incompletely defined multiple-valued logic functions is proposed. To compute these forms, discrete orthogonal transforms are used. The matrix and vector procedures are the foundation of the logic not polynomial form synthesis to represent multiple -valued functions. The main advantage of this forms is the possibility to investigate the properties of multiple-valued logical functions and to use the implementation of fast discrete orthogonal transforms for computation of analytical description coefficients. Genetic algorithms are applied to synthesize incompletely defined multiple valued functions.","PeriodicalId":403347,"journal":{"name":"Proceedings of 26th IEEE International Symposium on Multiple-Valued Logic (ISMVL'96)","volume":"115 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-01-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115743212","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
N. Muranaka, Shigenobu Arai, S. Imanishi, D. M. Miller
{"title":"A ternary systolic product-sum circuit for GF(3/sup m/) using neuron MOSFETs","authors":"N. Muranaka, Shigenobu Arai, S. Imanishi, D. M. Miller","doi":"10.1109/ISMVL.1996.508342","DOIUrl":"https://doi.org/10.1109/ISMVL.1996.508342","url":null,"abstract":"In this paper, we present a ternary systolic product-sum computation circuit for GF(3/sup m/) using voltage-mode neuron MOSFETs. The required subcircuits are discussed which together form a basic cell. The overall design which connects basic cells in a systolic manner, thereby making effective use of pipelining, is shown. SPICE simulations of the central part of the basic cell are presented which demonstrate its proper behaviour. The ternary circuit for GF(3/sup 2/) is compared to the binary circuit for GF(2/sup 3/) and is shown to be superior both in terms of the number of transistors and the number of connections.","PeriodicalId":403347,"journal":{"name":"Proceedings of 26th IEEE International Symposium on Multiple-Valued Logic (ISMVL'96)","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-01-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121687913","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
V. Shmerko, S. Yanushkevich, V. Levashenko, I. Bondar
{"title":"Technique of computing logic derivatives for MVL-functions","authors":"V. Shmerko, S. Yanushkevich, V. Levashenko, I. Bondar","doi":"10.1109/ISMVL.1996.508366","DOIUrl":"https://doi.org/10.1109/ISMVL.1996.508366","url":null,"abstract":"A technique to compute logic derivatives of MVL-functions is considered based on four algorithms, two of them are new. At first these are symbolic and matrix algorithms to find logic derivatives with respect to variables, and, secondly, partial direct and inverse derivatives. The algorithms are compared by using an example of testing a MVL switching circuit. The matrix approach allows to extract the appropriatenesses of computing process and to come to some simple operators of logic processing truth vectors of MVL functions.","PeriodicalId":403347,"journal":{"name":"Proceedings of 26th IEEE International Symposium on Multiple-Valued Logic (ISMVL'96)","volume":"301 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-01-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115219315","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"On the use of VHDL as a multi-valued logic simulator","authors":"C. Rozon","doi":"10.1109/ISMVL.1996.508345","DOIUrl":"https://doi.org/10.1109/ISMVL.1996.508345","url":null,"abstract":"This work demonstrates how VHDL can be used as a potential tool for the simulation of multi-valued digital circuits and systems. Although not all features of a given VHDL simulator can be applied to MVL signals, some can easily be adapted to provide enough information to verify functionality and/or timing specifications. The VHDL modelling and simulation of two simple ternary circuits are described and commented.","PeriodicalId":403347,"journal":{"name":"Proceedings of 26th IEEE International Symposium on Multiple-Valued Logic (ISMVL'96)","volume":"31 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-01-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130440246","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Reasoning in inconsistent stratified knowledge bases","authors":"S. Benferhat, D. Dubois, H. Prade","doi":"10.1109/ISMVL.1996.508357","DOIUrl":"https://doi.org/10.1109/ISMVL.1996.508357","url":null,"abstract":"This paper proposes a discussion of inconsistency-tolerant consequence relations in prioritized knowledge bases. These inference techniques extend methods for reasoning from inconsistent, non-stratified, knowledge bases to the case where priorities between formulas are available. Priorities between formulas are handled in the framework of possibility theory and allow for the use of pieces of information having various levels of confidence. A comparative analysis of several approaches is carried out, namely, the possibilistic inference and its extensions, three inference methods based on a selection of maximal consistent subsets of formulas, and two inference methods based on arguments.","PeriodicalId":403347,"journal":{"name":"Proceedings of 26th IEEE International Symposium on Multiple-Valued Logic (ISMVL'96)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-01-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116206800","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}