采用神经元mosfet的GF(3/sup m/)三元收缩积和电路

Proceedings of 26th IEEE International Symposium on Multiple-Valued Logic (ISMVL'96) Pub Date : 1996-01-19 DOI:10.1109/ISMVL.1996.508342

N. Muranaka, Shigenobu Arai, S. Imanishi, D. M. Miller

{"title":"采用神经元mosfet的GF(3/sup m/)三元收缩积和电路","authors":"N. Muranaka, Shigenobu Arai, S. Imanishi, D. M. Miller","doi":"10.1109/ISMVL.1996.508342","DOIUrl":null,"url":null,"abstract":"In this paper, we present a ternary systolic product-sum computation circuit for GF(3/sup m/) using voltage-mode neuron MOSFETs. The required subcircuits are discussed which together form a basic cell. The overall design which connects basic cells in a systolic manner, thereby making effective use of pipelining, is shown. SPICE simulations of the central part of the basic cell are presented which demonstrate its proper behaviour. The ternary circuit for GF(3/sup 2/) is compared to the binary circuit for GF(2/sup 3/) and is shown to be superior both in terms of the number of transistors and the number of connections.","PeriodicalId":403347,"journal":{"name":"Proceedings of 26th IEEE International Symposium on Multiple-Valued Logic (ISMVL'96)","volume":"52 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1996-01-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"10","resultStr":"{\"title\":\"A ternary systolic product-sum circuit for GF(3/sup m/) using neuron MOSFETs\",\"authors\":\"N. Muranaka, Shigenobu Arai, S. Imanishi, D. M. Miller\",\"doi\":\"10.1109/ISMVL.1996.508342\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper, we present a ternary systolic product-sum computation circuit for GF(3/sup m/) using voltage-mode neuron MOSFETs. The required subcircuits are discussed which together form a basic cell. The overall design which connects basic cells in a systolic manner, thereby making effective use of pipelining, is shown. SPICE simulations of the central part of the basic cell are presented which demonstrate its proper behaviour. The ternary circuit for GF(3/sup 2/) is compared to the binary circuit for GF(2/sup 3/) and is shown to be superior both in terms of the number of transistors and the number of connections.\",\"PeriodicalId\":403347,\"journal\":{\"name\":\"Proceedings of 26th IEEE International Symposium on Multiple-Valued Logic (ISMVL'96)\",\"volume\":\"52 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1996-01-19\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"10\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of 26th IEEE International Symposium on Multiple-Valued Logic (ISMVL'96)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISMVL.1996.508342\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of 26th IEEE International Symposium on Multiple-Valued Logic (ISMVL'96)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISMVL.1996.508342","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 10

摘要

本文采用电压型神经元mosfet，设计了GF(3/sup m/)的三元收缩积和计算电路。讨论了所需的子电路，它们共同构成一个基本单元。整体设计以收缩的方式连接基本细胞，从而有效地利用流水线。对基本单元的中心部分进行了SPICE模拟，证明了其正确的行为。GF(3/sup 2/)的三元电路与GF(2/sup 3/)的二进制电路相比，在晶体管数量和连接数量方面都表现出优越性。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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A ternary systolic product-sum circuit for GF(3/sup m/) using neuron MOSFETs

In this paper, we present a ternary systolic product-sum computation circuit for GF(3/sup m/) using voltage-mode neuron MOSFETs. The required subcircuits are discussed which together form a basic cell. The overall design which connects basic cells in a systolic manner, thereby making effective use of pipelining, is shown. SPICE simulations of the central part of the basic cell are presented which demonstrate its proper behaviour. The ternary circuit for GF(3/sup 2/) is compared to the binary circuit for GF(2/sup 3/) and is shown to be superior both in terms of the number of transistors and the number of connections.

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Proceedings of 26th IEEE International Symposium on Multiple-Valued Logic (ISMVL'96)

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