Proceedings of 26th IEEE International Symposium on Multiple-Valued Logic (ISMVL'96)最新文献

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On the lattice of partial clones on a finite set 有限集合上的部分克隆的格
L. Haddad, J. Fugère
{"title":"On the lattice of partial clones on a finite set","authors":"L. Haddad, J. Fugère","doi":"10.1109/ISMVL.1996.508367","DOIUrl":"https://doi.org/10.1109/ISMVL.1996.508367","url":null,"abstract":"Let A be a finite set with |A|/spl ges/2. We present some recent results on the lattice L/sub PA/spl circ// of partial clones on A.","PeriodicalId":403347,"journal":{"name":"Proceedings of 26th IEEE International Symposium on Multiple-Valued Logic (ISMVL'96)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-01-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124890228","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
The deepest repetition-free decompositions of nonsingular functions of finite-valued logics 有限值逻辑非奇异函数的深度无重复分解
F. Sokhatsky
{"title":"The deepest repetition-free decompositions of nonsingular functions of finite-valued logics","authors":"F. Sokhatsky","doi":"10.1109/ISMVL.1996.508368","DOIUrl":"https://doi.org/10.1109/ISMVL.1996.508368","url":null,"abstract":"A superposition is called repetition-free if every variable appears in it at most once. Two terms are said to almost coincide if the second term can be obtained from the first one in a finite number of steps: isotopy change, commutation change and associative change. The main result: every two deepest repetition-free decompositions of a nonsingular function of a finite-valued logics almost coincide. As a corollary we have the corresponding Kuznetaov's results for Boolean functions and Sosinsky's result for functions of three-valued logics.","PeriodicalId":403347,"journal":{"name":"Proceedings of 26th IEEE International Symposium on Multiple-Valued Logic (ISMVL'96)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-01-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125359467","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Wave-parallel computing technique for neural networks based on amplitude-modulated waves 基于调幅波的神经网络波并行计算技术
Y. Yuminaka, Y. Sasaki, T. Aoki, T. Higuchi
{"title":"Wave-parallel computing technique for neural networks based on amplitude-modulated waves","authors":"Y. Yuminaka, Y. Sasaki, T. Aoki, T. Higuchi","doi":"10.1109/ISMVL.1996.508360","DOIUrl":"https://doi.org/10.1109/ISMVL.1996.508360","url":null,"abstract":"Wave-parallel computing (WPC) technique is proposed to address the interconnection problem in massively interconnected VLSI architectures required for implementing artificial neural networks. The fundamental concepts are frequency multiplexing of signals on a single line, and their wave-parallel processing without decomposition. This paper discusses the realization of a Hopfield-type fully connected neural network as an example, and shows that the WPC-based network exhibits much lower topological complexity compared with the original network. We also investigate the possible implementation of WPC based on the present MOS technology, and discuss the evaluation in terms of the degree of multiplexing and processing speed.","PeriodicalId":403347,"journal":{"name":"Proceedings of 26th IEEE International Symposium on Multiple-Valued Logic (ISMVL'96)","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-01-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122364704","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Efficiently irreducible bases in multiple-valued logic 多值逻辑中的有效不可约基
Grant R. Pogosyan
{"title":"Efficiently irreducible bases in multiple-valued logic","authors":"Grant R. Pogosyan","doi":"10.1109/ISMVL.1996.508371","DOIUrl":"https://doi.org/10.1109/ISMVL.1996.508371","url":null,"abstract":"Basis is a functionally complete set of multiple-valued logic functions that is irreducible, i.e. contains no complete proper subsets. Functional completeness of a set means that for any function in MVL there exists a formula over this set that implements it. However, this classical definition of basis does not consider the efficiency of implementation, particularly, it does not guarantee the existence of an efficient implementation regarding the complexity of formal expressions. In this note the notion of efficiently irreducible basis is introduced, and is termed /spl epsiv/-basis. A criterion for the basic set of operations to be efficiently irreducible is given. In the cases of Boolean and ternary logic functions complete enumeration and description of /spl epsiv/-bases are presented.","PeriodicalId":403347,"journal":{"name":"Proceedings of 26th IEEE International Symposium on Multiple-Valued Logic (ISMVL'96)","volume":"12 6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-01-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123798855","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Weight structures for approximate reasoning with weighted expressions 用加权表达式近似推理的权结构
Stephan Lehmke
{"title":"Weight structures for approximate reasoning with weighted expressions","authors":"Stephan Lehmke","doi":"10.1109/ISMVL.1996.508373","DOIUrl":"https://doi.org/10.1109/ISMVL.1996.508373","url":null,"abstract":"One method of constructing an 'approximate reasoning' system is to use a 'classical' system of many-valued logic and attach to each logical expression a 'weight' which assesses the validity of this expression. Several such systems have been described in the literature, with varying interpretations concerning structure and semantics of weights. In this paper, a 'canonical' principle for defining the fundamental relations model and semantic consequence for logics with weighted expressions is described, which not only allows a large variety of truth-value and weight structures, but furthermore allows to transfer the results of 'classical' model theory to the resulting logics in a natural way.","PeriodicalId":403347,"journal":{"name":"Proceedings of 26th IEEE International Symposium on Multiple-Valued Logic (ISMVL'96)","volume":"109 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-01-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114561768","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A literal gate using resonant-tunneling devices 使用共振隧道装置的文字门
T. Waho, K. J. Chen, Masafumi Yamamoto
{"title":"A literal gate using resonant-tunneling devices","authors":"T. Waho, K. J. Chen, Masafumi Yamamoto","doi":"10.1109/ISMVL.1996.508338","DOIUrl":"https://doi.org/10.1109/ISMVL.1996.508338","url":null,"abstract":"We propose a novel literal gate consisting of one resonant-tunneling diode (RTD) and two resonant-tunneling transistors (RTTs). Logic operation is based on the control of the switching sequence of these devices through the modulation of their peak currents by the input signal. By using an integrated RTD-HEMT pair as an RTT, we implement literal gates and successfully obtain the literal function. A modified literal gate that allows us to vary literal-window width even after completing device fabrication is also demonstrated.","PeriodicalId":403347,"journal":{"name":"Proceedings of 26th IEEE International Symposium on Multiple-Valued Logic (ISMVL'96)","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-01-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121510436","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Logic expressions of monotonic multiple-valued functions 单调多值函数的逻辑表达式
K. Nakashima, Y. Nakamura, N. Takagi
{"title":"Logic expressions of monotonic multiple-valued functions","authors":"K. Nakashima, Y. Nakamura, N. Takagi","doi":"10.1109/ISMVL.1996.508370","DOIUrl":"https://doi.org/10.1109/ISMVL.1996.508370","url":null,"abstract":"This paper presents some fundamental properties of multiple-valued logic functions monotonic with respect to a partial-ordering relation which is introduced in the set of truth values and does not necessarily have the greatest or least element. Two kinds of necessary and sufficient conditions for monotonic p-valued functions are given with the proofs. Their logic formulas using unary operators defined in the partial-ordering relation and a simplification method for those logic formulas are also given. These results include our former results for p-valued functions monotonic with respect to the ambiguity relation which is a partial-ordering relation with the greatest element.","PeriodicalId":403347,"journal":{"name":"Proceedings of 26th IEEE International Symposium on Multiple-Valued Logic (ISMVL'96)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-01-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117326845","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Design of one-vector testable binary systems based on ternary logic 基于三元逻辑的单向量可测试二进制系统的设计
Mou Hu
{"title":"Design of one-vector testable binary systems based on ternary logic","authors":"Mou Hu","doi":"10.1109/ISMVL.1996.508337","DOIUrl":"https://doi.org/10.1109/ISMVL.1996.508337","url":null,"abstract":"A new concept, one-vector testability, is defined. Design method to achieve one-vector testability of binary systems based on ternary logic is proposed. Some techniques for designing testable binary systems based on ternary circuits are re-examined by using the proposed design method.","PeriodicalId":403347,"journal":{"name":"Proceedings of 26th IEEE International Symposium on Multiple-Valued Logic (ISMVL'96)","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-01-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115099801","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Verification of multi-valued logic networks 多值逻辑网络的验证
R. Drechsler
{"title":"Verification of multi-valued logic networks","authors":"R. Drechsler","doi":"10.1109/ISMVL.1996.508329","DOIUrl":"https://doi.org/10.1109/ISMVL.1996.508329","url":null,"abstract":"A method for verification of Multi-Valued Logic Networks (MVLNs) using Ordered Multi-Valued Decision Diagrams (OMDDs) is presented. For tree-like MVLNs an upper bound on the OMDD size can be proven. Thus, heuristics known for OBDDs can also be used for OMDDs. A large set of experiments is presented that underlines the efficiency of the approach.","PeriodicalId":403347,"journal":{"name":"Proceedings of 26th IEEE International Symposium on Multiple-Valued Logic (ISMVL'96)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-01-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132501985","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 25
Associativeness versus recursiveness 联想性与递归性
V. Cutello, E. Molina, J. Montero
{"title":"Associativeness versus recursiveness","authors":"V. Cutello, E. Molina, J. Montero","doi":"10.1109/ISMVL.1996.508353","DOIUrl":"https://doi.org/10.1109/ISMVL.1996.508353","url":null,"abstract":"Fuzzy connectives used to be assumed associative. In this way, key operational difficulties are solved by means of a single binary operator. In this paper we point out that the main property in order to assure operativeness should be recursiveness, which is weaker than associativity. If calculus can be obtained by means of a recursive application of a sequence of binary connectives, we still can develop operative models. It is then clearly seen that a fuzzy role should be always understood as a family of fuzzy connectives. Associativity will appear when a fuzzy rule can be characterized by a single binary connective. Associativity assumption is therefore excluding from our model key rules in practice.","PeriodicalId":403347,"journal":{"name":"Proceedings of 26th IEEE International Symposium on Multiple-Valued Logic (ISMVL'96)","volume":"124 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-01-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123187926","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
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