{"title":"基于三元逻辑的单向量可测试二进制系统的设计","authors":"Mou Hu","doi":"10.1109/ISMVL.1996.508337","DOIUrl":null,"url":null,"abstract":"A new concept, one-vector testability, is defined. Design method to achieve one-vector testability of binary systems based on ternary logic is proposed. Some techniques for designing testable binary systems based on ternary circuits are re-examined by using the proposed design method.","PeriodicalId":403347,"journal":{"name":"Proceedings of 26th IEEE International Symposium on Multiple-Valued Logic (ISMVL'96)","volume":"62 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1996-01-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Design of one-vector testable binary systems based on ternary logic\",\"authors\":\"Mou Hu\",\"doi\":\"10.1109/ISMVL.1996.508337\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A new concept, one-vector testability, is defined. Design method to achieve one-vector testability of binary systems based on ternary logic is proposed. Some techniques for designing testable binary systems based on ternary circuits are re-examined by using the proposed design method.\",\"PeriodicalId\":403347,\"journal\":{\"name\":\"Proceedings of 26th IEEE International Symposium on Multiple-Valued Logic (ISMVL'96)\",\"volume\":\"62 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1996-01-19\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of 26th IEEE International Symposium on Multiple-Valued Logic (ISMVL'96)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISMVL.1996.508337\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of 26th IEEE International Symposium on Multiple-Valued Logic (ISMVL'96)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISMVL.1996.508337","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Design of one-vector testable binary systems based on ternary logic
A new concept, one-vector testability, is defined. Design method to achieve one-vector testability of binary systems based on ternary logic is proposed. Some techniques for designing testable binary systems based on ternary circuits are re-examined by using the proposed design method.