On the use of VHDL as a multi-valued logic simulator

Abstract

This work demonstrates how VHDL can be used as a potential tool for the simulation of multi-valued digital circuits and systems. Although not all features of a given VHDL simulator can be applied to MVL signals, some can easily be adapted to provide enough information to verify functionality and/or timing specifications. The VHDL modelling and simulation of two simple ternary circuits are described and commented.