浅谈使用VHDL作为多值逻辑模拟器

Proceedings of 26th IEEE International Symposium on Multiple-Valued Logic (ISMVL'96) Pub Date : 1996-01-19 DOI:10.1109/ISMVL.1996.508345

C. Rozon

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引用次数: 10

摘要

这项工作证明了VHDL如何被用作多值数字电路和系统仿真的潜在工具。尽管并非给定VHDL模拟器的所有功能都可以应用于MVL信号，但有些功能可以很容易地进行调整，以提供足够的信息来验证功能和/或时序规范。对两个简单三元电路的VHDL建模和仿真进行了描述和评论。

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On the use of VHDL as a multi-valued logic simulator

This work demonstrates how VHDL can be used as a potential tool for the simulation of multi-valued digital circuits and systems. Although not all features of a given VHDL simulator can be applied to MVL signals, some can easily be adapted to provide enough information to verify functionality and/or timing specifications. The VHDL modelling and simulation of two simple ternary circuits are described and commented.

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Proceedings of 26th IEEE International Symposium on Multiple-Valued Logic (ISMVL'96)

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