{"title":"An array based system for real time buffer management","authors":"G. Konstantoulakis, D. Reisis","doi":"10.1109/ICECS.1996.582740","DOIUrl":"https://doi.org/10.1109/ICECS.1996.582740","url":null,"abstract":"This work describes a real time array-based memory managing module. The techniques shown here lead to the efficient utilization of computer buffers as well as buffers used in communication switches for high speed broadband networks. In both cases, the memory manager can serve in real time the requests from the external computer system providing a memory bandwidth in the range of gigabits. The design uses a 2-dimensional array with 1-bit processing elements, which further involves row and column buses. The memory within each processing element varies in magnitude from 1-bit to the size of the array. There are two realisations of the system described in the paper, the first with 1-bit memory and the second with k-bit memory per processing element.","PeriodicalId":402369,"journal":{"name":"Proceedings of Third International Conference on Electronics, Circuits, and Systems","volume":"129 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121495843","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Low-power image decoding using fractals","authors":"K. Masselos, P. Merakos, T. Stouraitis, C. Goutis","doi":"10.1109/ICECS.1996.584470","DOIUrl":"https://doi.org/10.1109/ICECS.1996.584470","url":null,"abstract":"In this paper a low-power evaluation of image decoding using fractals is presented. Fractal coding is asymmetrical in nature meaning that the encoder and the decoder have not the same computational complexity. Although fractal encoding is very complex in terms of computation, the computational requirements of fractal decoding are very small favoring low power consumption. Structural algorithmic properties of fractal decoding also favor low-power. Comparison with other classical decoding techniques shows that significant power savings can be achieved by using fractal decoding. This is very important for portable applications if the fact that the decoder is usually the mobile part of a system is taken into consideration.","PeriodicalId":402369,"journal":{"name":"Proceedings of Third International Conference on Electronics, Circuits, and Systems","volume":"175 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122649243","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A new method, using the graph theoretical approach, for obtaining symbolic state equations of linear electronic circuits","authors":"J. P. Baron, Erwan Cadran","doi":"10.1109/ICECS.1996.582625","DOIUrl":"https://doi.org/10.1109/ICECS.1996.582625","url":null,"abstract":"The state-space modelling of linear time-invariant electronic circuits without degeneracies is considered in this paper. The principal idea is to represent an electronic circuit as the interconnection of several integrators. A special type of directed graph (digraph) is used to describe the electronic circuit from the topological equations (voltages and currents) and the equations of component parts. An algorithm based on the analysis of this digraph is proposed which directly obtains the symbolic matrices of the state-space model of the circuit. From this digraph, various symbolic transfer function equations can be generated that express the desired relationships between variables of interest. The algorithm to find symbolic transfer function produces the results of the well-known Mason's reduction formula. A topological interpretation of sensitivity has been made to obtain symbolic sensitivity functions easily.","PeriodicalId":402369,"journal":{"name":"Proceedings of Third International Conference on Electronics, Circuits, and Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131114340","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
H. Ahmad, A. Al-Khalili, L. Landsberger, M. Kahrizi
{"title":"A 2D micromachined accelerometer","authors":"H. Ahmad, A. Al-Khalili, L. Landsberger, M. Kahrizi","doi":"10.1109/ICECS.1996.584532","DOIUrl":"https://doi.org/10.1109/ICECS.1996.584532","url":null,"abstract":"A surface micromachined 2-D accelerometer is designed and implemented in CMOS. The implementation requires the addition of three masking steps to a commercially available standard CMOS process. It has a /spl plusmn/100 g full range reading and better than 1% linearity within this range with a sensitivity of 0.5 mV/g. The signal detection circuitry is an on-chip switched capacitor charge transfer circuit operating on an internally generated 1 MHz four-phase non-overlapping clock.","PeriodicalId":402369,"journal":{"name":"Proceedings of Third International Conference on Electronics, Circuits, and Systems","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132532064","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Recursive optimization of an extended Fisher discriminant criterion","authors":"M. Aladjem","doi":"10.1109/ICECS.1996.584460","DOIUrl":"https://doi.org/10.1109/ICECS.1996.584460","url":null,"abstract":"A method for recursive optimization of an extended Fisher (ExF) discriminant criterion is proposed. The method consists of obtaining a discriminant direction which optimizes the ExF criterion, transforming the data along it into data with greater class overlap, and iterating to obtain the next discriminant direction. An application to a medical dataset indicates the potential of the proposed method for finding a sequence of oblique directions with significant class separation.","PeriodicalId":402369,"journal":{"name":"Proceedings of Third International Conference on Electronics, Circuits, and Systems","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131807259","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"General-purpose piecewise-linear DC analysis","authors":"J. Roos, M. Valtonen","doi":"10.1109/ICECS.1996.584481","DOIUrl":"https://doi.org/10.1109/ICECS.1996.584481","url":null,"abstract":"Finding the DC solution of a nonlinear circuit is one of the most important tasks in circuit simulation. The convergence problems of the conventional DC analysis can be partly avoided by using piecewise-linear analysis. In the traditional piecewise-linear DC analysis, nonlinear components must be first approximated with continuous piecewise-linear functions. In this paper a new piecewise-linear DC analysis method, where piecewise-linear modeling of nonlinear components is combined with analysis, is proposed. The method proposed has been implemented in the APLAC circuit simulator.","PeriodicalId":402369,"journal":{"name":"Proceedings of Third International Conference on Electronics, Circuits, and Systems","volume":"87 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134450717","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Interfacing optical memories and electronic computers","authors":"L. J. Irakliotis, G. Betzos, P. Mitkas","doi":"10.1109/ICECS.1996.582933","DOIUrl":"https://doi.org/10.1109/ICECS.1996.582933","url":null,"abstract":"Recent advances in optical storage technology, both two-dimensional and three-dimensional, suggest that optical memories can be used for applications requiring massive archiving volumes. In order to use optical memories in such applications we need to interface them with electronic computers. Our paper discusses the aspects of this interface design.","PeriodicalId":402369,"journal":{"name":"Proceedings of Third International Conference on Electronics, Circuits, and Systems","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134623426","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A new matching approach based on line moments in binocular stereovision","authors":"J. Brochard, M. Khoudeir, C. Eliot, T. Simon","doi":"10.1109/ICECS.1996.584455","DOIUrl":"https://doi.org/10.1109/ICECS.1996.584455","url":null,"abstract":"This paper concern the matching phase needed in binocular stereovision, for object location in 3D scene. We present here a new matching approach exploiting line moments. We show that the relation between the line moments having (0+q) order of a segment of the image on the right and the same order moment of the image on the left keep a constant value if the two considered segments are well matched. This relation becomes variable in the case of a bad matching. This method have been tested on diverse real scenes with varied complexity levels and the results obtained are presented.","PeriodicalId":402369,"journal":{"name":"Proceedings of Third International Conference on Electronics, Circuits, and Systems","volume":"76 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115516765","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
G. Theodoridis, S. Theoharis, D. Soudris, O. Koufopavlou, C. Goutis
{"title":"A novel approach for reducing the switching activity in two-level logic circuits","authors":"G. Theodoridis, S. Theoharis, D. Soudris, O. Koufopavlou, C. Goutis","doi":"10.1109/ICECS.1996.584513","DOIUrl":"https://doi.org/10.1109/ICECS.1996.584513","url":null,"abstract":"A new approach for implementing two-level logic circuits, which exhibit minimal power dissipation, is presented. Switching activity reduction of the logic network nodes is achieved by adding in specific gates additional input signals. By using the statistical properties of the primary inputs, a new concept for grouping the input variables with similar features is presented. An efficient synthesis algorithm for generating the set of all classes of the variables and for solving the minimum covering problem for each class is introduced. The comparison of the results, produced by the proposed method, and those from ESPRESSO shows that a significant power reduction can be achieved for the two-level logic circuits.","PeriodicalId":402369,"journal":{"name":"Proceedings of Third International Conference on Electronics, Circuits, and Systems","volume":"28 2","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114126815","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Estimation of articulatory synthesiser parameters from pseudo-formants","authors":"H. Altun, K. M. Curtis","doi":"10.1109/ICECS.1996.584654","DOIUrl":"https://doi.org/10.1109/ICECS.1996.584654","url":null,"abstract":"The articulatory speech synthesiser is likely to be the ultimate solution to the synthesis of natural sounding, intelligible speech. Yet, the problem of estimating articulatory parameters, from a given speech signal, remains a challenge although remarkable attempts have been reported within the literature towards this end. This paper presents a new technique for the accurate estimation of articulatory parameters through the use of \"pseudo formants\" and their corresponding amplitudes.","PeriodicalId":402369,"journal":{"name":"Proceedings of Third International Conference on Electronics, Circuits, and Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114315825","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}