{"title":"一个基于数组的实时缓冲区管理系统","authors":"G. Konstantoulakis, D. Reisis","doi":"10.1109/ICECS.1996.582740","DOIUrl":null,"url":null,"abstract":"This work describes a real time array-based memory managing module. The techniques shown here lead to the efficient utilization of computer buffers as well as buffers used in communication switches for high speed broadband networks. In both cases, the memory manager can serve in real time the requests from the external computer system providing a memory bandwidth in the range of gigabits. The design uses a 2-dimensional array with 1-bit processing elements, which further involves row and column buses. The memory within each processing element varies in magnitude from 1-bit to the size of the array. There are two realisations of the system described in the paper, the first with 1-bit memory and the second with k-bit memory per processing element.","PeriodicalId":402369,"journal":{"name":"Proceedings of Third International Conference on Electronics, Circuits, and Systems","volume":"129 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1996-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"An array based system for real time buffer management\",\"authors\":\"G. Konstantoulakis, D. Reisis\",\"doi\":\"10.1109/ICECS.1996.582740\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This work describes a real time array-based memory managing module. The techniques shown here lead to the efficient utilization of computer buffers as well as buffers used in communication switches for high speed broadband networks. In both cases, the memory manager can serve in real time the requests from the external computer system providing a memory bandwidth in the range of gigabits. The design uses a 2-dimensional array with 1-bit processing elements, which further involves row and column buses. The memory within each processing element varies in magnitude from 1-bit to the size of the array. There are two realisations of the system described in the paper, the first with 1-bit memory and the second with k-bit memory per processing element.\",\"PeriodicalId\":402369,\"journal\":{\"name\":\"Proceedings of Third International Conference on Electronics, Circuits, and Systems\",\"volume\":\"129 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1996-10-13\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of Third International Conference on Electronics, Circuits, and Systems\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICECS.1996.582740\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of Third International Conference on Electronics, Circuits, and Systems","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICECS.1996.582740","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
An array based system for real time buffer management
This work describes a real time array-based memory managing module. The techniques shown here lead to the efficient utilization of computer buffers as well as buffers used in communication switches for high speed broadband networks. In both cases, the memory manager can serve in real time the requests from the external computer system providing a memory bandwidth in the range of gigabits. The design uses a 2-dimensional array with 1-bit processing elements, which further involves row and column buses. The memory within each processing element varies in magnitude from 1-bit to the size of the array. There are two realisations of the system described in the paper, the first with 1-bit memory and the second with k-bit memory per processing element.