A novel approach for reducing the switching activity in two-level logic circuits

Abstract

A new approach for implementing two-level logic circuits, which exhibit minimal power dissipation, is presented. Switching activity reduction of the logic network nodes is achieved by adding in specific gates additional input signals. By using the statistical properties of the primary inputs, a new concept for grouping the input variables with similar features is presented. An efficient synthesis algorithm for generating the set of all classes of the variables and for solving the minimum covering problem for each class is introduced. The comparison of the results, produced by the proposed method, and those from ESPRESSO shows that a significant power reduction can be achieved for the two-level logic circuits.