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Error analysis of FFT architectures for digital video applications 数字视频应用中FFT结构的误差分析
Proceedings of Third International Conference on Electronics, Circuits, and Systems Pub Date : 1996-10-13 DOI: 10.1109/ICECS.1996.584488
C. Hui, T. J. Ding, J. McCanny, Roger Francis Woods
{"title":"Error analysis of FFT architectures for digital video applications","authors":"C. Hui, T. J. Ding, J. McCanny, Roger Francis Woods","doi":"10.1109/ICECS.1996.584488","DOIUrl":"https://doi.org/10.1109/ICECS.1996.584488","url":null,"abstract":"Describes how worst-case error analysis can be applied to solve some of the practical issues in the development and implementation of a low power, high performance radix-4 FFT chip for digital video applications. The chip has been fabricated using a 0.6 /spl mu/m CMOS technology and can perform a 64 point complex forward or inverse FFT on real-time video at up to 18 Megasamples per second. It comprises 0.5 million transistors in a die area of 7.8/spl times/8 mm/sup 2/ and dissipates IW, leading to a cost-effective silicon solution for high quality video processing applications. The analysis focuses on the effect that different radix-4 architectural configurations and finite wordlengths has on the FFT output dynamic range. These issues are addressed using both mathematical error models and through extensive simulation.","PeriodicalId":402369,"journal":{"name":"Proceedings of Third International Conference on Electronics, Circuits, and Systems","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114486294","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Motion estimation and DCT pruning: a combined approach to video coding 运动估计和DCT剪枝:一种视频编码的组合方法
Proceedings of Third International Conference on Electronics, Circuits, and Systems Pub Date : 1996-10-13 DOI: 10.1109/ICECS.1996.584467
Dimitris Kalles, A. Skodras
{"title":"Motion estimation and DCT pruning: a combined approach to video coding","authors":"Dimitris Kalles, A. Skodras","doi":"10.1109/ICECS.1996.584467","DOIUrl":"https://doi.org/10.1109/ICECS.1996.584467","url":null,"abstract":"In the present communication an approach to the performance optimization of an H.261 implementation is described. Discrete Cosine Transform (DCT) coefficient pruning is employed and its effect on motion estimation strategies is studied. This interplay produces some very interesting experimental results on the trade-off between quality and speed of video coding.","PeriodicalId":402369,"journal":{"name":"Proceedings of Third International Conference on Electronics, Circuits, and Systems","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114741801","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Systolic array prototyping using the Ptolemy environment 使用托勒密环境的收缩阵列原型
Proceedings of Third International Conference on Electronics, Circuits, and Systems Pub Date : 1996-10-13 DOI: 10.1109/ICECS.1996.584449
Theodore Kaskalis, K. Margaritis
{"title":"Systolic array prototyping using the Ptolemy environment","authors":"Theodore Kaskalis, K. Margaritis","doi":"10.1109/ICECS.1996.584449","DOIUrl":"https://doi.org/10.1109/ICECS.1996.584449","url":null,"abstract":"In this paper we present an example of how the Ptolemy environment can be used constructively to implement and simulate systolic algorithms and architectures. Through graphical means, the user can easily obtain systolic circuit prototypes in a level high enough to be comprehensive and, at the same time, low enough to present the design complexity of a potential implementation. Moreover, the ability to simulate the functioning of the circuit ensures the correctness of a systolic algorithm. A brief introduction to the Ptolemy environment is given and a step by step creation of two typical systolic array designs is then described. A hierarchical design method is followed and details are given about the correct reflection of the synchronous nature of systolic circuits on typical dataflow executions.","PeriodicalId":402369,"journal":{"name":"Proceedings of Third International Conference on Electronics, Circuits, and Systems","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116228779","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Research and innovation: a new route to development 研究创新:发展新路子
Proceedings of Third International Conference on Electronics, Circuits, and Systems Pub Date : 1996-10-13 DOI: 10.1109/ICECS.1996.584659
F. Maloberti
{"title":"Research and innovation: a new route to development","authors":"F. Maloberti","doi":"10.1109/ICECS.1996.584659","DOIUrl":"https://doi.org/10.1109/ICECS.1996.584659","url":null,"abstract":"Electronics and microelectronics affect modern societies in an extremely pervasive manner. The impact is so relevant as to make electronic disciplines not only a technical or an industrial topic, but also a political and a social issue. This poses a key and controversial question: can high-technology (electronics and microelectronics), contribute to development? The answer is not direct and unique: it may or it may not, and all depends on policies followed and national and regional strategies. This paper through a contemporary and historical perspective, raises certain points which will hopefully contribute to future debate.","PeriodicalId":402369,"journal":{"name":"Proceedings of Third International Conference on Electronics, Circuits, and Systems","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115156820","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
On the efficacy of sampled-data modelling of switched networks 交换网络采样数据建模的有效性研究
Proceedings of Third International Conference on Electronics, Circuits, and Systems Pub Date : 1996-10-13 DOI: 10.1109/ICECS.1996.582913
R. Tymerski
{"title":"On the efficacy of sampled-data modelling of switched networks","authors":"R. Tymerski","doi":"10.1109/ICECS.1996.582913","DOIUrl":"https://doi.org/10.1109/ICECS.1996.582913","url":null,"abstract":"The limitations of sampled-data modelling in determining frequency response of switched networks such as switching power converters are highlighted. A general scheme for constructing small-signal difference equations used in sampled-data models is given. This scheme overcomes the limitations of current approaches used in obtaining input-to-output responses. However, in common with all other sampled-data modelling approaches, problems of accuracy and appropriate choice of formulation of difference equations still remain. Consequently, use of sampled-data models to determine frequency response is not recommended. However, the difference equation formulation scheme developed here may be used in a small-signal describing function modelling approach which is here demonstrated to be accurate, have no ambiguity of use and no frequency limitations in contrast to sampled-data modelling.","PeriodicalId":402369,"journal":{"name":"Proceedings of Third International Conference on Electronics, Circuits, and Systems","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123392899","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Optimization and efficient implementation of fractional delay FIR filters 分数阶延迟FIR滤波器的优化与高效实现
Proceedings of Third International Conference on Electronics, Circuits, and Systems Pub Date : 1996-10-13 DOI: 10.1109/ICECS.1996.582926
J. Vesma, T. Saramäki
{"title":"Optimization and efficient implementation of fractional delay FIR filters","authors":"J. Vesma, T. Saramäki","doi":"10.1109/ICECS.1996.582926","DOIUrl":"https://doi.org/10.1109/ICECS.1996.582926","url":null,"abstract":"An efficient design method is introduced for optimizing polynomial-based fractional delay filters. For these filters, the worst-case amplitude distortion occurs in the given passband when the delay is half the sampling interval. The corresponding discrete-time filter is optimized to minimize the passband amplitude distortion, binding some degrees of freedom. The remaining degrees of freedom are used for minimizing the worst-case deviation of the phase delay response from the desired delay value. Because these filters are polynomial-based, they can be efficiently implemented using the so-called Farrow structure.","PeriodicalId":402369,"journal":{"name":"Proceedings of Third International Conference on Electronics, Circuits, and Systems","volume":"136 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123257936","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Neural networks arbitration for automatic edge detection of 3-dimensional objects 三维物体自动边缘检测的神经网络仲裁
Proceedings of Third International Conference on Electronics, Circuits, and Systems Pub Date : 1996-10-13 DOI: 10.1109/ICECS.1996.582661
A. Khashman, K. M. Curtis
{"title":"Neural networks arbitration for automatic edge detection of 3-dimensional objects","authors":"A. Khashman, K. M. Curtis","doi":"10.1109/ICECS.1996.582661","DOIUrl":"https://doi.org/10.1109/ICECS.1996.582661","url":null,"abstract":"The use of Neural Networks for edge detection is in its infancy, and has not as yet been applied in Multiscale analysis. Multiscale edge detection offers a very effective solution to a wide range of feature extraction problems. The work so far reported has focused on region extraction and edge detection of 2-Dimensional objects. Here the noise and illumination effects on the images are less than would be found in the case of a 3-Dimensional object. In the work reported in this paper both the quality of the detected edges and the introduction of the noise and illumination effects due to the third dimension will be considered. This paper reports on investigations into the use of scale space analysis for 3-Dimensional object recognition. The results are then used to form the basis for the use of a Neural Network to carry out Automatic Edge detection, by defining the correct scale at which to apply the Fast Laplacian of the Gaussian operator, during scale space analysis.","PeriodicalId":402369,"journal":{"name":"Proceedings of Third International Conference on Electronics, Circuits, and Systems","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123531767","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
Real-time emulation of DSP applications on programmable DSPs and FPGAs DSP应用在可编程DSP和fpga上的实时仿真
Proceedings of Third International Conference on Electronics, Circuits, and Systems Pub Date : 1996-10-13 DOI: 10.1109/ICECS.1996.582928
R. Lauwereins, M. Adé, S. Note
{"title":"Real-time emulation of DSP applications on programmable DSPs and FPGAs","authors":"R. Lauwereins, M. Adé, S. Note","doi":"10.1109/ICECS.1996.582928","DOIUrl":"https://doi.org/10.1109/ICECS.1996.582928","url":null,"abstract":"The paper describes the RETIDES design flow and building blocks which allow for fast and cost-effective prototyping of complete DSP systems on heterogeneous re-usable hardware platforms consisting of general purpose DSP processors, core processors and field programmable gate arrays. Early experiences with two classes of industrial audio and speech applications are reported.","PeriodicalId":402369,"journal":{"name":"Proceedings of Third International Conference on Electronics, Circuits, and Systems","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123633508","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Two correction schemes for the minimization of the severe non-linear distortion introduced by an ADPCM link 针对ADPCM链路引入的严重非线性失真，提出了两种校正方案
Proceedings of Third International Conference on Electronics, Circuits, and Systems Pub Date : 1996-10-13 DOI: 10.1109/ICECS.1996.582814
S. Jimaa, B. Woodward
{"title":"Two correction schemes for the minimization of the severe non-linear distortion introduced by an ADPCM link","authors":"S. Jimaa, B. Woodward","doi":"10.1109/ICECS.1996.582814","DOIUrl":"https://doi.org/10.1109/ICECS.1996.582814","url":null,"abstract":"The paper is concerned with serial data transmission at a rate of 9600 bit/s over a telephone channel containing a 32 kbit/s Adaptive Differential Pulse Code Modulation (ADPCM) link. The transmitted data signal is a 2400 baud 16-level (QAM) signal. The ADPCM link introduces time varying and at times severe nonlinear distortion into the data signal. The two correction schemes described, known here as system A and system B, operate by attempting to correct the nonlinear distortion. The correction may be applied either at the transmitter or at the receiver, and in either case it may operate on the baseband or on the bandpass signal. The most promising scheme studied operates on the received bandpass signal at the receiver. Results of computer simulation tests are presented. Some tests use a decision feedback equalizer and others use a near-maximum likelihood detector at the receiver. The results show that the most significant improvement can be gained by using system A with the near-maximum likelihood detector.","PeriodicalId":402369,"journal":{"name":"Proceedings of Third International Conference on Electronics, Circuits, and Systems","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122542476","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Mixed-signal circuit testing-A review 混合信号电路测试综述
Proceedings of Third International Conference on Electronics, Circuits, and Systems Pub Date : 1996-10-13 DOI: 10.1109/ICECS.1996.584604
C. Wey
{"title":"Mixed-signal circuit testing-A review","authors":"C. Wey","doi":"10.1109/ICECS.1996.584604","DOIUrl":"https://doi.org/10.1109/ICECS.1996.584604","url":null,"abstract":"Testing and fault diagnosis are two important aspects in the design and maintenance of mixed-signal circuits. To enhance testability and fault diagnosability, both design-for-testability (DFT) and built-in self-test (BIST) techniques have been successfully developed for digital circuits. This paper reviews the development of these techniques in analog circuits and discusses the future challenges in both fault diagnosis and testing.","PeriodicalId":402369,"journal":{"name":"Proceedings of Third International Conference on Electronics, Circuits, and Systems","volume":"164 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123860376","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
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