Proceedings of Topical Workshop on Electronics for Particle Physics — PoS(TWEPP2018)最新文献

{"title":"Characterization of the first prototype of the Silicon-Strip readout ASIC (SSA) for the CMS Outer-Tracker phase-2 upgrade","authors":"Alessandro Caratelli, S. Scarfi, D. Ceresa, K. Kloukinas, J. Kapłon, J. Clercq, M. Haranko, Y. Leblebici","doi":"10.22323/1.343.0159","DOIUrl":"https://doi.org/10.22323/1.343.0159","url":null,"abstract":"The silicon strip readout ASIC (SSA) for the CMS Outer Tracker Pixel-Strip (PS) module was prototyped in a 65nm CMOS technology and characterized utilizing a custom made test bench based on the FC7 µTCA FPGA card. The ASIC has been evaluated and characterized under different working temperatures and radiation levels up to 200Mrad. Measurements show a frontend gain between 35 and 54mV/fC and an average noise of <330e-, meeting the specification of noise performance. The measured peaking time for an injected charge between 0.5fC and 8fC is 19ns allowing to detect consecutive particle events in combination with the zero dead-cycle binary readout. The embedded trimming circuit allows to obtain a measured threshold spread smaller than 55e- between channels. The measured power consumption is 60mW and thus within the strict power budget of the PS modules. The performance characterization results and radiation tolerance test results of the first SSA silicon prototype are presented.","PeriodicalId":400748,"journal":{"name":"Proceedings of Topical Workshop on Electronics for Particle Physics — PoS(TWEPP2018)","volume":"63 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123472017","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"The VMM front-end integration in the Scalable Readout System: On the way to a next generation readout system for generic detector R&D and experiment instrumentation","authors":"M. Lupberger, Freddy Fuentes Robayo, Y. Huang, S. Martoiu, H. Muller, D. Pfeiffer, A. Rusu","doi":"10.22323/1.343.0136","DOIUrl":"https://doi.org/10.22323/1.343.0136","url":null,"abstract":"Michael Lupberger*† CERN, Geneva, Switzerland E-mail: michael.lupberger@cern.ch Freddy Fuentes Robayo Universidad Antonio Narino, Bogota, Columbia Yan Huang Central China Normal University, Wuhan, China Sorin Martoiu Horia Hulubei National Institute of Physics and Nuclear Engineering, Magurele, Bucharest, Romania Hans Müller CERN, Geneva, Switzerland Dorothea Pfeiffer CERN, Geneva, Switzerland and European Spallation Source ERIC, Lund, Sweden Alexandru Rusu Horia Hulubei National Institute of Physics and Nuclear Engineering, Magurele, Bucharest, Romania The Scalable Readout System (SRS) of the RD51 collaboration with the APV25 ASIC is driving R&D for gaseous detectors. Discontinuation of APV25 and demands on flexibility concerning e.g. detector capacitance and readout rate induced a replacement of the ASIC, for which the collaboration has chosen the VMM chip of the ATLAS New Small Wheel upgrade. A prototype SRS VMM system was operated with small GEM detectors at test beams and hardware components are finalised. More than twelve groups signed as primary system users. We present the readout chain and current status of the implementation of the VMM in SRS, applications and further developments. Topical Workshop on Electronics for Particle Physics (TWEPP2018) 17-21 September 2018 Antwerp, Belgium","PeriodicalId":400748,"journal":{"name":"Proceedings of Topical Workshop on Electronics for Particle Physics — PoS(TWEPP2018)","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123003078","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"New LpGBT-FPGA IP: Simulation model and first implementation","authors":"J. Mendez, S. Baron, S. Kulis, J. Fonseca","doi":"10.22323/1.343.0059","DOIUrl":"https://doi.org/10.22323/1.343.0059","url":null,"abstract":"High-speed links are commonly used in High Energy Physics experiments for data acquisition, trigger and timing distribution. For this reason, a radiation-hard link is being developed in order to match the increasing bandwidth demand of the backend electronics and computing systems. In this framework, the LpGBT - which is the evolution of the GBTx SERDES - is being designed and is foreseen to be installed in CMS and ATLAS for Phase-2 upgrades. The LpGBT-FPGA IP core is proposed to offer a backend counterpart of the LpGBT. This paper presents the IP architecture, the status of its development and future steps.","PeriodicalId":400748,"journal":{"name":"Proceedings of Topical Workshop on Electronics for Particle Physics — PoS(TWEPP2018)","volume":"106 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123888139","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Operation of the CMS Level-1 Calorimeter Trigger in High Pileup Conditions and Motivations for Phase-2","authors":"A. Bundock","doi":"10.22323/1.343.0126","DOIUrl":"https://doi.org/10.22323/1.343.0126","url":null,"abstract":"To maintain high trigger efficiencies and stable rates during significant changes to beam conditions throughout 2017, the CMS Level-1 calorimeter trigger required dynamic and flexible operation. Successfully running since 2015, utilising Xilinx Virtex 7 690 FPGAs and 10 Gbps optical links, the versatile design has enabled quick adaption to improve algorithms to mitigate large rates from high pileup and changes in detector response, and as the LHC responded to a number of unexpected challenges. Operational experience and lessons learned will be discussed, and how they will inform important decisions in the design and implementation of the Phase-2 trigger upgrade.","PeriodicalId":400748,"journal":{"name":"Proceedings of Topical Workshop on Electronics for Particle Physics — PoS(TWEPP2018)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121190625","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Service hybrids for the silicon strip modules of the CMS Phase-2 Outer Tracker upgrade","authors":"L. Feld, M. Wlochal, Nicolas Maximilian Roewert, K. Klein, G. Pierschel, M. Preuten, W. Karpinski, M. Rauch, A. Pauls","doi":"10.22323/1.343.0127","DOIUrl":"https://doi.org/10.22323/1.343.0127","url":null,"abstract":"","PeriodicalId":400748,"journal":{"name":"Proceedings of Topical Workshop on Electronics for Particle Physics — PoS(TWEPP2018)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117198256","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"ABACUS : Two fast amplifiers for the readout of LGAD detectors","authors":"G. Mazza, F. Fausti, J. Olave, V. Monaco, R. Sacchi, R. Cirio","doi":"10.22323/1.343.0071","DOIUrl":"https://doi.org/10.22323/1.343.0071","url":null,"abstract":": The design of a single particle counter for therapeutical proton beams based on Low Gain Avalanche Diodes optimized for very fast signals is carried on in the framework of the INFN MoveIt research project. Fast signal shaping front­end electronics is mandatory in this application in order to deal with particle rates of the order of hundreds of MHz. Two preamplifier architectures, one based on a fast Charge Sensitive Amplifier with self­reset capabilities and a second one based on a Trans­Impedance Amplifier have been developed in a commercial CMOS 0.11 μm technology and submitted to the foundry. a INFN sezione di Torino, 10125 Torino, Italy b Politecnico di Torino, 10129 Torino, Italy c Università di Torino, Dipartimento di Fisica, 10125 Torino, Italy R. Cirio, F. Fausti, G. Mazza, V. Monaco, J. Olave, R. Sacchi Low Gain Avalanche Diode (LGAD) Requirement : fast counting rate (100 MHz or better fast rise time → not sufficient,the full signal shape must be short. Two configurations under evaluation : 1. Charge Sensitive Amplifier (CSA) 2. TransImpedance Amplifier (TIA) CSA : fast rising time and lower noise than TIA, but the falling edge can be slow self reset capability → TIA : faster but also higher noise. Trade off between bandwidth, open loop gain and input capacitance f −3dB≈ 1 2π A RF CD 1. CSA preamplfier 2. OTA buffer 3. Discriminator stage 1 4. Discriminator stage 2 5. Single­ended to diff converter 6. CML driver 7. Threshold tuning DAC (6­bit) 8. Pulse generator 9. Recovery block 10. Inverters CSA­based readout channel TIA­based readout channel 1. Transimpedance preamplifier 2. Gain stage 3. Discriminator 4. CML driver 5. Discriminator differential threshold generator Transimpedance Amplifier architectures Two stages core amplifier with global resistive feedback : ✔ Higher open loop gain ✗ Sensitive to input capacitance variations ✗ Differential input Single stage core amplifier driven by a current buffer : ✔ TIA input capacitance independent from detector capacitance ✔ Single ended input ✗ No gain on the first stage Simulation result examples Two detectors under test : length 15 mm, width 80 μm, pitch 146 μm and length 30 mm, width 150 μm, pitch 216 μm Input capacitance C D ~ 3­6 pF Signal (protons) : 4­150 fC (with gain 15) Signal (carbon ions) : 30­150 fC (with gain 1) Input data obtained from Weightfield2 and GEANT simulations for the predicted environment. Average particle rate per channel are 50, 100, 150, 200 and 250 MHz. Post layout simulations detail for the CSA channel for 100 and 200 MHz and 60 MeV and 250 MeV proton energy. Post layout simulations for the TIA v1 channel at 200 MHz rate. Proton energy 250 MeV. Summary and outlook  Two 24­channels prototypes for the fast count of particles crossing a LGAD silicon detector have been designed and produced.  The first prototype is based on a charge sensitive amplier with self­reset  The second prototype is based on a transimpedance amplifier architecture. Two sub­version of t","PeriodicalId":400748,"journal":{"name":"Proceedings of Topical Workshop on Electronics for Particle Physics — PoS(TWEPP2018)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116131706","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A possible implementation of a detector specific extension of the FELIX firmware for the ITk Pixel sub-detector","authors":"C. Duelsen, Tobias Flick, W. Wagner, M. Wensing","doi":"10.22323/1.343.0064","DOIUrl":"https://doi.org/10.22323/1.343.0064","url":null,"abstract":"For the ATLAS Phase-II upgrade, a completely new all-silicon inner tracker is planned, which will be read out at higher bandwidth due to finer granularity and higher occupancy. At that point, the detector readout will be switched to the new ATLAS wide readout system focusing on the usage of the GBT protocol and introducing the FELIX concept. While the ITk Pixel sub-detector allows the usage of the GBT protocol on the downlink path, it needs a different uplink protocol due to certain constrains. This work shows how a detector specific extension of the FELIX firmware could look like and which blocks are needed for the ITk Pixel sub-detector.","PeriodicalId":400748,"journal":{"name":"Proceedings of Topical Workshop on Electronics for Particle Physics — PoS(TWEPP2018)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125578249","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"CMS ECAL Upgrade Front End card: design and prototype test results","authors":"A. Singovski, A. Dolgopolov, C. Jessop, N. Loukas","doi":"10.22323/1.343.0044","DOIUrl":"https://doi.org/10.22323/1.343.0044","url":null,"abstract":"vGoal: Ømaintain ECAL performance in LHC Phase II environment (pileup, high radiation ) ØImprove detector functionality for spike tagging, pileup resolution, triggering vSolution: ØReplace readout electronics üHigh sampling rate üNo-dead-time data streaming üHigh performance off-detector readout processor ØDetector components: PWO crystals and APDs will continue to perform well and remain unchanged Phase II ECAL Upgrade","PeriodicalId":400748,"journal":{"name":"Proceedings of Topical Workshop on Electronics for Particle Physics — PoS(TWEPP2018)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131910395","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Front-end Electronics of the Forward Strip Detector for the ATLAS HL-LHC Upgrade","authors":"Carlos Garcia Argos, A. Greenall, M. Hauser, K. Jakobs, K. Mahboubi, U. Parzefal, L. Wiik-Fuchs, S. Wonsak","doi":"10.22323/1.343.0014","DOIUrl":"https://doi.org/10.22323/1.343.0014","url":null,"abstract":"The ATLAS ITk Strip Detector I All-silicon detector with around 70 million read-out strips. I Modular design with modules assembled into larger structures: staves and petals. I Four barrel layers and six end-cap discs per side. I Integrated cooling, power and read-out electronics. I We present here the construction and testing of prototype hybrids for rings 0, 1, 3, 4 and 5. I Read-out chips glued and wire-bonded onto the hybrids. I ABC (ATLAS Binary Chip) analogue read-out chip connected to the strips, sends data to HCC. I HCC (Hybrid Controller Chip) digital read-out chip sends data from ABC to the DAQ. I Forward region uses “Stereo Annulus” shaped sensors and modules, arranged in rings. I Different number of strips leads to different number of front-end read-out chips. I Changing strip pitch and length for each segment. Sketch of a Petal","PeriodicalId":400748,"journal":{"name":"Proceedings of Topical Workshop on Electronics for Particle Physics — PoS(TWEPP2018)","volume":"461 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132996110","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Radiation hardness test of the nSYNC ASIC with 60 MeV proton beam","authors":"D. Brundu, S. Cadeddu, A. Cardini, L. Casu","doi":"10.22323/1.343.0124","DOIUrl":"https://doi.org/10.22323/1.343.0124","url":null,"abstract":"The nSYNC chip is a radiation tolerant custom ASIC, developed in UMC 130 nm technology for the upgrade of the readout electronics of the LHCb Muon System. The chip will work, over ten years of upgrade operation, in a radioactive environment and exposed to a total dose of 13 krad and a fluence of 2 · 1012 cm 2 1-MeV neutrons equivalent. The results of radiation tests performed at the Catana facility (INFN Laboratori Nazionali del Sud) with 60 MeV proton beam are discussed, with a particular focus on the internal logic and TDC performance, and Single Event Effects measurements.","PeriodicalId":400748,"journal":{"name":"Proceedings of Topical Workshop on Electronics for Particle Physics — PoS(TWEPP2018)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121722256","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}