Journal of Integrated Circuits and Systems最新文献_第2页

Improvement of AlGaN/ GaN based HEMT with high performance rate for integrated circuit design for wide range of applications 改进基于氮化铝/氮化镓的 HEMT，使其具有更高的性能，适用于各种应用的集成电路设计

Journal of Integrated Circuits and Systems Pub Date : 2024-03-15 DOI: 10.29292/jics.v19i1.747

Swati Dhondiram Jadhav, Aboo Bakar Khan

{"title":"Improvement of AlGaN/ GaN based HEMT with high performance rate for integrated circuit design for wide range of applications","authors":"Swati Dhondiram Jadhav, Aboo Bakar Khan","doi":"10.29292/jics.v19i1.747","DOIUrl":"https://doi.org/10.29292/jics.v19i1.747","url":null,"abstract":"In the current research work, we focused on the design and analysis of a semiconductor device called High-Elec-tron-Mobility Transistor (HEMT) based on the AlGaN/GaN material system. An Aluminum Nitride spacer,Layer of Nucle-ation along with cap as a AlGaN and barrier of GaN with the channel of AlGaN are incorporated to enhance HEMT device performance.The electrical characteristics of the proposed HEMT are an-alyzed. The Drain Current is found to be 0.18A/mm, indicating the device's ability to handle high current levels. The Electron Concentration is observed to have a maximum value of -96.12electrons/cm3 and varying based on the position in the channel for GaN Barrier thickness is 0.15mm. In the analysis of AC such as Gain of the Maximum Unilateral Power is deter-mined to be 83.41dB, indicating the ability of the device to am-plify signals. The Y-parameters, which characterize the de-vice's behavior at various frequencies of operation, are also de-termined. The capacitance between the electrode region Gate-Source (CGSMIN) is found to be 1.70×10^-11 F/mm, and alike The Capacitance between the electrode region the Gate-Drain Ca-pacitance (CGDMIN) is determined to be 4.7×10^-12 F/mm. Fur-thermore, an Electric Field of 96.51×10^3 V/mm is observed, in-dicating the strength of the electric field across the device. For HEMT device the simulation,The TCAD Silvaco software is be-ing practiced.","PeriodicalId":39974,"journal":{"name":"Journal of Integrated Circuits and Systems","volume":" 23","pages":""},"PeriodicalIF":0.0,"publicationDate":"2024-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140392256","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Parameter extraction using the transfer characteristics of vertically stacked Si nanosheet MOSFETs 利用垂直堆叠硅纳米片 MOSFET 的传输特性提取参数

Journal of Integrated Circuits and Systems Pub Date : 2024-03-15 DOI: 10.29292/jics.v19i1.801

A. Ortiz-Conde, V. C. P. Silva, Anabela Veloso, P. Agopian, Simoen Eddy, Joao A. Martino, F. García-Sánchez

引用次数: 0

Hetero-Structure Junctionless MOSFET with High-k Corner Spacer for High-Speed and Energy-Efficient Applications 采用高 k 角垫片的异质结构无结 MOSFET，适用于高速和高能效应用

Journal of Integrated Circuits and Systems Pub Date : 2024-03-15 DOI: 10.29292/jics.v19i1.796

Mainak Mukherjee, Niloy Ghosh, Papiya Debnath, A. Sarkar, M. Chanda

引用次数: 0

Efficient 3’s Complement Circuit for Ternary-ALU 三元-ALU 的高效 3 的补码电路

Journal of Integrated Circuits and Systems Pub Date : 2024-03-15 DOI: 10.29292/jics.v19i1.750

Aloke Saha, Sudeshna Dutta, Snigdha Dutta, Osman Hossain Siddique, Rimpa Dey, Anup Kumar Das

{"title":"Efficient 3’s Complement Circuit for Ternary-ALU","authors":"Aloke Saha, Sudeshna Dutta, Snigdha Dutta, Osman Hossain Siddique, Rimpa Dey, Anup Kumar Das","doi":"10.29292/jics.v19i1.750","DOIUrl":"https://doi.org/10.29292/jics.v19i1.750","url":null,"abstract":"Carrying more information makes the ternary-computation effective in order to reduce the interconnect complexity and hence, ternary computer can be the future alternative to conventional (binary) counterpart. As a consequence the ternary arithmetic has become the centre of choice among circuit/system researcher in recent time. Ternary adder/subtractor is the integral part of Ternary Arithmetic Logic Unit (TALU) and the 3’s complement is used to represent negative ternary number in TALU. This work proposes a new two-step low hardware-cost strategy to converts ternary input into its 3’s complement output. Novel hardware optimization using normal process Enhancement-type Metal Oxide Semiconductor (E-MOS)-transistor is explored and exploited to design proposed 4-trit 3’s complement generator on 32nm standard CMOS technology with 0.9V supply-rail at 27°C temperature using typical MOS-transistor. Unbalanced ternary digit “0”, “1” and “2” are denoted with ground, supply/2 and supply respectively. The T-Spice transient simulations with all possible test patterns validate the working of proposed circuit and the corresponding speed-power characteristic is compared with most recent counterpart. The circuit performance is also evaluated with different load condition. The 4-trit 3’s complement circuit is extended next to propose 16-trit 3’s complement generator and the impact of Process and Environmental variation on the proposed circuit is studied.","PeriodicalId":39974,"journal":{"name":"Journal of Integrated Circuits and Systems","volume":" 2","pages":""},"PeriodicalIF":0.0,"publicationDate":"2024-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140391914","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Small-Signal Modeling and Parameter Extraction Method for Photovoltaic Cell Integration in Indoor Visible Light Communication Systems 室内可见光通信系统中光伏电池集成的小信号建模和参数提取方法

Journal of Integrated Circuits and Systems Pub Date : 2024-03-15 DOI: 10.29292/jics.v19i1.763

Diego Mattos, Vitoria Monteiro, P. D. de Aguirre, Lucas Severo, Alessandro Girardi

{"title":"Small-Signal Modeling and Parameter Extraction Method for Photovoltaic Cell Integration in Indoor Visible Light Communication Systems","authors":"Diego Mattos, Vitoria Monteiro, P. D. de Aguirre, Lucas Severo, Alessandro Girardi","doi":"10.29292/jics.v19i1.763","DOIUrl":"https://doi.org/10.29292/jics.v19i1.763","url":null,"abstract":"Photovoltaic (PV) cells are being adopted as a viable and cost-effective option for implementing receivers within Visible Light Communication (VLC) systems, primarily in indoor environments. Accurately estimating the generated current and voltage of the PV cell based on incident light is crucial when designing VLC systems.For this assessment, the 1D2R electrical equivalent model, which incorporates a diode and two resistors, is employed.In AC small signal analysis, the diode is substituted by its dynamic counterpart, which comprises a dynamic resistance in parallel with an equivalent capacitance. This study introduces an approach to measure and characterize the small-signal parameters of a PV cell operating at the maximum power point (MPP), open circuit (OC), and short circuit (SC) bias points. This is achieved through a closed-loop frequency response system, calibrated to encompass illuminance levels ranging from 50 to 500 lux.The procedure for estimating the AC response of the PV cell is outlined, and the outcomes are subsequently employed in an analytical parameter extraction methodology. Experimental results from a 20 x 40 mm PV cell reveal that MPP represents the least favorable bias point in terms of bandwidth, whereas the SC bias point exhibits the most favorable performance. This observation validates the hypothesis that the optimal bias point for energy harvesting in PV cells is the worst bias point for communication purposes.","PeriodicalId":39974,"journal":{"name":"Journal of Integrated Circuits and Systems","volume":" 15","pages":""},"PeriodicalIF":0.0,"publicationDate":"2024-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140391935","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Improved GaN-based Current Aperture Vertical Electron Transistor (CAVET) 改进型gan型电流孔径垂直电子晶体管(CAVET)

Journal of Integrated Circuits and Systems Pub Date : 2023-09-27 DOI: 10.29292/jics.v18i2.680

HADJEM Dalila, Zakarya KOURDI, Imane FOUR, KERAI Salim, KHAOUANI Mohammed

引用次数: 0

Comparative Analysis of Sinusoidal Oscillators with Surface Acoustic Wave Sensor in the Feedback Loop 反馈回路中正弦波振荡器与表面声波传感器的对比分析

Journal of Integrated Circuits and Systems Pub Date : 2023-09-27 DOI: 10.29292/jics.v18i2.690

Henrique Silva, Raimundo Carlos Silvério Freire, Jalberth Fernandes de Araújo, Sávio Correia Bezerra, Maria Nathália Freitas Nunes, Maxence Rube, Ollivier Tamarin

{"title":"Comparative Analysis of Sinusoidal Oscillators with Surface Acoustic Wave Sensor in the Feedback Loop","authors":"Henrique Silva, Raimundo Carlos Silvério Freire, Jalberth Fernandes de Araújo, Sávio Correia Bezerra, Maria Nathália Freitas Nunes, Maxence Rube, Ollivier Tamarin","doi":"10.29292/jics.v18i2.690","DOIUrl":"https://doi.org/10.29292/jics.v18i2.690","url":null,"abstract":"Surface acoustic wave sensors can be implemented within the feedback loop of sinusoidal oscillators for detecting pollutants. This detection process involves analyzing the variation of oscillator output voltage parameters, such as amplitude and oscillation frequency. However, each oscillator topology has a distinct operating range concerning frequency and component values. Therefore, a comparative analysis is necessary to determine the oscillator with optimal performance to use with the sensor. To obtain results, a surface acoustic wave sensor model was chosen based on a piezoelectric crystal with a resonant frequency of 117.6 MHz, and three sinusoidal oscillator topologies were used: Pierce, Colpitts, and Clapp. The oscillators were simulated with the sensor model in the feedback loop using the Montecarlo method. The simulation occurred in two steps: individually varying each component by +/- 20% with 250 iterations, and simultaneously varying all components by +/- 20% with 1000 iterations. The variables analyzed in the simulations were amplitude, oscillation frequency, and a new parameter indicating the percentage of time there is an oscillation, termed \"robustness.\" As a result, it was determined that all three oscillators generated oscillations in the output voltage, making them viable for use with the sensor. Furthermore, it was discovered that the Clapp oscillator had a robustness of 84.5%, while the Colpitts and Pierce oscillators had a robustness of 56.3% and 49.9%, respectively. Therefore, based on the results presented in this study, the Clapp oscillator is the optimal choice for use with the surface acoustic wave sensor.","PeriodicalId":39974,"journal":{"name":"Journal of Integrated Circuits and Systems","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-09-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"135586112","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Three inputs and one output voltage-mode universal biquadratic filter using one CCII and one CCIII 使用一个CCII和一个CCIII的三输入一输出电压模式通用双二次滤波器

Journal of Integrated Circuits and Systems Pub Date : 2023-09-27 DOI: 10.29292/jics.v18i2.633

Jiun-Wei Horng

引用次数: 0

Multiplexer Based Error Efficient Fixed-Width Adder Tree Design for Signal Processing Applications 信号处理应用中基于多路复用器的误差高效定宽加法器树设计

Journal of Integrated Circuits and Systems Pub Date : 2023-09-27 DOI: 10.29292/jics.v18i2.691

None Rashmi Seethur, None Deeksha Sudarshan, None Vaibhavi Naik, None Tushar Masur, None Shreedhar H K

{"title":"Multiplexer Based Error Efficient Fixed-Width Adder Tree Design for Signal Processing Applications","authors":"None Rashmi Seethur, None Deeksha Sudarshan, None Vaibhavi Naik, None Tushar Masur, None Shreedhar H K","doi":"10.29292/jics.v18i2.691","DOIUrl":"https://doi.org/10.29292/jics.v18i2.691","url":null,"abstract":"In copious mixed media applications, humans cannot necessarily discern error free or erroneous outputs, owing to the small range of perception abilities. Crucial information can still be obtained from marginally inexact outputs. Leveraging this, many algorithms such as Digital Signal Processing (DSP), Discrete Cosine Transform (DCT), Motion Compensation (MC) use approximate calculations while still maintaining appreciable computation accuracy. When data processing algorithms are taken into consideration, adders play an important role in the arithmetic module by managing the power and area utilization of the system. A fixed-width adder tree design for approximate calculations is proposed, that uses the trade-off between area and accuracy as the base for analysis. Our design uses 12.42%, 18.17% and 5.05% lesser area compared to the full width adder tree, FX-AT-PT and FX-AT-DT respectively. Additionally, when compared to FX-AT-DT, TFX-AT and ITFX-AT, the proposed design has an improved Maximum Error Distance (MED) of (33.33%, 29.03%), (63.64%, 65.63%) and (38.46%, 35.29%) for N = 8, 16 respectively. To cope with the inaccuracy caused by truncation, the proposed design employs mux-based radix-4 addition coupled with bias estimation. Further, to examine the error performance we have incorporated the proposed design and a few other existing designs into the Walsh-Hadamard Transform (WHT), to process images with different metrics and compare the Peak Signal to Noise Ratio (PSNR) of the images. It was observed that the proposed design showed significant improvement in the PSNR score when compared to ITFX-AT and maintains a score similar to that of FX-AT-PT.","PeriodicalId":39974,"journal":{"name":"Journal of Integrated Circuits and Systems","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-09-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"135586113","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Pre-processing of ECG signal based on multistage filters 基于多级滤波的心电信号预处理

Journal of Integrated Circuits and Systems Pub Date : 2023-09-27 DOI: 10.29292/jics.v18i2.698

Mohammed Waheed

引用次数: 0