Journal of Integrated Circuits and Systems最新文献_第10页

Review on Variable and Programmable Gain Amplifiers and Applications 可变增益和可编程增益放大器及其应用综述

Journal of Integrated Circuits and Systems Pub Date : 2022-04-30 DOI: 10.29292/jics.v17i1.583

Michel Santana de Deus, Sebastian Yuri Cavalcanti Catunda, Antônio Wallace Antunes Soares, Diomadson Rodrigues Belfort

引用次数: 0

Are CMOS Operational Transconductance Amplifiers Old Fashioned? A Systematic Review CMOS操作跨导放大器过时了吗?系统回顾

Journal of Integrated Circuits and Systems Pub Date : 2022-04-30 DOI: 10.29292/jics.v17i1.574

Rodrigo Aparecido da Silva Braga, Paulo M. Moreira e Silva, Dean Bicudo Karolak

引用次数: 0

A Low-cost Fault Tolerance Method for ARM and RISC-V Microprocessor-based Systems using Temporal Redundancy and Approximate Computing through Simplified Iterations 基于时间冗余和简化迭代近似计算的ARM和RISC-V微处理器系统低成本容错方法

Journal of Integrated Circuits and Systems Pub Date : 2022-04-02 DOI: 10.29292/jics.v16i3.539

Alexander Aponte-Moreno, Felipe Restrepo-Calle, C. Pedraza

{"title":"A Low-cost Fault Tolerance Method for ARM and RISC-V Microprocessor-based Systems using Temporal Redundancy and Approximate Computing through Simplified Iterations","authors":"Alexander Aponte-Moreno, Felipe Restrepo-Calle, C. Pedraza","doi":"10.29292/jics.v16i3.539","DOIUrl":"https://doi.org/10.29292/jics.v16i3.539","url":null,"abstract":"Approximate Computing techniques have been successfully used to reduce the overhead associated with redundancy in fault-tolerant system designs. This paper presents a fault tolerance method to reduce the execution time overhead of the well-known Time Redundancy technique by means of an improvement proposed for the Approximate Computing software-based technique known as loop perforation. Time Redundancy is a software-based fault tolerance technique that involves executing replicas of a task at different times. We propose to approximate the tasks to be executed using a new approximate computing technique based on loop perforation, i.e., simplified iterations. The novelty of this method is the combined use of the fault tolerance technique, temporal redundancy, jointly with the new proposed Approximate Computing technique, simplified iterations. The proposal is validated through simulation-based fault injection campaigns on several test programs for the ARM and RISC-V microprocessor architectures. Experimental results verified not only the applicability of the proposal in different architectures, but also its effectiveness, showing a good trade-off between reliability, error and overhead. Results showed that using the proposed method, a normalized mean work to failure (MWTF) up to 5.28× was obtained with approximation errors lower than those obtained using the traditional loop perforation technique.","PeriodicalId":39974,"journal":{"name":"Journal of Integrated Circuits and Systems","volume":" ","pages":""},"PeriodicalIF":0.0,"publicationDate":"2022-04-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"47368076","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

ANFIS Based Thermal Estimation of Ultradeep Submicron Digital Circuit Design 基于ANFIS的超深亚微米数字电路设计热估计

Journal of Integrated Circuits and Systems Pub Date : 2022-02-07 DOI: 10.29292/jics.v16i3.507

Ruby Beniwal, Shruti Kalra

{"title":"ANFIS Based Thermal Estimation of Ultradeep Submicron Digital Circuit Design","authors":"Ruby Beniwal, Shruti Kalra","doi":"10.29292/jics.v16i3.507","DOIUrl":"https://doi.org/10.29292/jics.v16i3.507","url":null,"abstract":"In this paper, the use of the Adaptive Neuro Fuzzy Inference System (ANFIS) to model the CMOS inverter is discussed as a tool for developing and simulating CMOS logic circuits at the ultradeep submicron technology node of 22nm. The ANFIS structures are built and trained using MATLAB software. The ANFIS network was trained using data obtained from the analytical model (at 298.15K and 398.15K). For training, two methodologies are used: a hybrid learning method based on back-propagation and least-squares estimation, and back-propagation. The effect of the ANFIS model's structure on the accuracy and performance of the CMOS inverter has also been investigated. Further, simulation through HSPICE using (Predictive Technology Model) PTM nominal parameters has been done to compare with ANFIS (trained using an analytical model) results. The comparison of ANFIS and HSPICE suggests the ANFIS modelling procedure's practicality and correctness. The findings demonstrate that the ANFIS simulation is significantly faster and more comparable than the HSPICE simulation and that it can be easily integrated into software tools for designing and simulating complicated CMOS logic circuits.","PeriodicalId":39974,"journal":{"name":"Journal of Integrated Circuits and Systems","volume":" ","pages":""},"PeriodicalIF":0.0,"publicationDate":"2022-02-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"45163123","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Guest Editors' Words 特邀编辑的话

Journal of Integrated Circuits and Systems Pub Date : 2022-02-03 DOI: 10.29292/jics.v16i3.575

Fernanda Lima Kastensmidt, S. C. Asensi

引用次数: 0

Reliability analysis of gamma- and X-ray TID effects, on a commercial AlGaN/GaN based FET 商用AlGaN/GaN基场效应管γ -和x -射线TID效应的可靠性分析

Journal of Integrated Circuits and Systems Pub Date : 2021-12-31 DOI: 10.29292/jics.v16i3.566

A. C. Vilas Bôas, Saulo Gabriel Alberton, Nilberto H. Medina, Vitor Ângelo Paulino, Marco Antonio Assis Melo, Roberto Baginski Santos, R. Giacomini, T. Cavalcante, Rafael Galhardo Vaz, E. Junior, L. Seixas, S. Finco, M. Guazzelli

引用次数: 2

A Multi-Stage TIA based on Cascoded-Inverter Structures for Low-power Applications 用于低功率应用的基于级联逆变器结构的多级TIA

Journal of Integrated Circuits and Systems Pub Date : 2021-12-31 DOI: 10.29292/jics.v16i3.520

Sima Honarmand, M. Pourahmadi, M. Shayesteh, K. Abbasi

引用次数: 1

A 0.25-V Three-stage State Feedback Bulk-driven OTA for Wide Range Load Applications 用于宽负载应用的0.25-V三级状态反馈体驱动OTA

Journal of Integrated Circuits and Systems Pub Date : 2021-12-31 DOI: 10.29292/jics.v16i3.498

Sreeteja Reddy Kotha, Karuppanan P, A. K. Gautam, Manmath Suryavanshi

{"title":"A 0.25-V Three-stage State Feedback Bulk-driven OTA for Wide Range Load Applications","authors":"Sreeteja Reddy Kotha, Karuppanan P, A. K. Gautam, Manmath Suryavanshi","doi":"10.29292/jics.v16i3.498","DOIUrl":"https://doi.org/10.29292/jics.v16i3.498","url":null,"abstract":"This article employs a nested state feedback compensation technique to a three-stage bulk-driven operational transconductance amplifier (OTA). The projected OTA circuit consists of a bulk-driven PMOS amplifier, gate-driven NMOS amplifier, and common source (CS) amplifier. The entire transistors in the amplifier core are configuredwith self-cascode transistor topology to increase its output impedance. All transistors are designed to operate in a weak inversion in order to dissipate less power. Cross-coupled transistor pair topology in the bulk-driven stage allows to improve the effective transconductance of OTA. The CS amplifier can drive a large load capacitor. The polarities and transconductance gains of feedback blocks are controlled appropriately to obtain the desired DC gain and bandwidth. The capacitor-less compensation strategy allows the fabrication of the OTA using the minimum area. Conventional bulk-driven miler OTA, Bulk-driven stage improved indirect-feedback OTA (BSIF OTA), Gate-driven stage added bulk-driven OTA (GSIF OTA), and proposed bulk-driven OTA topologies are designed and simulated using cadence spectre tool at 25 mV supply voltage in the 65nm CMOS process. These OTA circuits are analyzed and compared in terms of parameters like DC gain, unity-gain frequency, phase margin, CMRR, power dissipated, slew rate, and input referred noise.","PeriodicalId":39974,"journal":{"name":"Journal of Integrated Circuits and Systems","volume":" ","pages":""},"PeriodicalIF":0.0,"publicationDate":"2021-12-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"46606760","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Survey on Reliability Estimation in Digital Circuits 数字电路可靠性估计研究进展

Journal of Integrated Circuits and Systems Pub Date : 2021-12-31 DOI: 10.29292/jics.v16i3.568

Matheus Ferreira Pontes, Clayton R. Farias, R. Schvittz, P. Butzen, Leomar Da Rosa Jr.

{"title":"Survey on Reliability Estimation in Digital Circuits","authors":"Matheus Ferreira Pontes, Clayton R. Farias, R. Schvittz, P. Butzen, Leomar Da Rosa Jr.","doi":"10.29292/jics.v16i3.568","DOIUrl":"https://doi.org/10.29292/jics.v16i3.568","url":null,"abstract":"The aggressive technology scaling has significantly affected the circuit reliability. The interaction of environmental radiation with the devices in the integrated circuits (ICs) may be the dominant reliability aspect of advanced ICs. Several techniques have been explored to mitigate the radiation effects and guarantee a satisfactory reliability levels. In this context, estimating circuit radiation reliability is crucial and a challenge that has not yet been overcome. For decades, several different methods have been proposed to provide circuit reliability. Recently, the radiation effects have been more faithfully incorporated in these strategies to provide the circuit susceptibility more accurately. This paper overviews the current trend for estimating the radiation reliability of digital circuits. The survey divides the approaches into two abstraction levels: (i) gate-level that incorporate the layout information and (ii) circuit-level that traditionally explore the logic circuit characteristic to provide the radiation susceptibility of combinational circuits. We also present an open-source tool that incorporates several previously explored methods. Finally, the actual research aspects are discussed, providing the newly emerging topic, such as selective hardening and critical vector identification.","PeriodicalId":39974,"journal":{"name":"Journal of Integrated Circuits and Systems","volume":" ","pages":""},"PeriodicalIF":0.0,"publicationDate":"2021-12-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"42914166","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

Effects of Thermal Annealing on the Density of States in Low Voltage Operating Range, High Mobility, Hf-In-ZnO/HfO2 TFTs Fabricated at Temperatures below 200 oC 低温退火对低电压高迁移率Hf-In-ZnO/HfO2 tft态密度的影响

Journal of Integrated Circuits and Systems Pub Date : 2021-12-31 DOI: 10.29292/jics.v16i3.561

I. Hernández, I. Garduño, A. Cerdeira, B. Iñíguez, M. Estrada

引用次数: 1