Sreeteja Reddy Kotha, Karuppanan P, A. K. Gautam, Manmath Suryavanshi
{"title":"用于宽负载应用的0.25-V三级状态反馈体驱动OTA","authors":"Sreeteja Reddy Kotha, Karuppanan P, A. K. Gautam, Manmath Suryavanshi","doi":"10.29292/jics.v16i3.498","DOIUrl":null,"url":null,"abstract":"This article employs a nested state feedback compensation technique to a three-stage bulk-driven operational transconductance amplifier (OTA). The projected OTA circuit consists of a bulk-driven PMOS amplifier, gate-driven NMOS amplifier, and common source (CS) amplifier. The entire transistors in the amplifier core are configuredwith self-cascode transistor topology to increase its output impedance. All transistors are designed to operate in a weak inversion in order to dissipate less power. Cross-coupled transistor pair topology in the bulk-driven stage allows to improve the effective transconductance of OTA. The CS amplifier can drive a large load capacitor. The polarities and transconductance gains of feedback blocks are controlled appropriately to obtain the desired DC gain and bandwidth. The capacitor-less compensation strategy allows the fabrication of the OTA using the minimum area. Conventional bulk-driven miler OTA, Bulk-driven stage improved indirect-feedback OTA (BSIF OTA), Gate-driven stage added bulk-driven OTA (GSIF OTA), and proposed bulk-driven OTA topologies are designed and simulated using cadence spectre tool at 25 mV supply voltage in the 65nm CMOS process. These OTA circuits are analyzed and compared in terms of parameters like DC gain, unity-gain frequency, phase margin, CMRR, power dissipated, slew rate, and input referred noise.","PeriodicalId":39974,"journal":{"name":"Journal of Integrated Circuits and Systems","volume":" ","pages":""},"PeriodicalIF":0.0000,"publicationDate":"2021-12-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"A 0.25-V Three-stage State Feedback Bulk-driven OTA for Wide Range Load Applications\",\"authors\":\"Sreeteja Reddy Kotha, Karuppanan P, A. K. Gautam, Manmath Suryavanshi\",\"doi\":\"10.29292/jics.v16i3.498\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This article employs a nested state feedback compensation technique to a three-stage bulk-driven operational transconductance amplifier (OTA). The projected OTA circuit consists of a bulk-driven PMOS amplifier, gate-driven NMOS amplifier, and common source (CS) amplifier. The entire transistors in the amplifier core are configuredwith self-cascode transistor topology to increase its output impedance. All transistors are designed to operate in a weak inversion in order to dissipate less power. Cross-coupled transistor pair topology in the bulk-driven stage allows to improve the effective transconductance of OTA. The CS amplifier can drive a large load capacitor. The polarities and transconductance gains of feedback blocks are controlled appropriately to obtain the desired DC gain and bandwidth. The capacitor-less compensation strategy allows the fabrication of the OTA using the minimum area. Conventional bulk-driven miler OTA, Bulk-driven stage improved indirect-feedback OTA (BSIF OTA), Gate-driven stage added bulk-driven OTA (GSIF OTA), and proposed bulk-driven OTA topologies are designed and simulated using cadence spectre tool at 25 mV supply voltage in the 65nm CMOS process. These OTA circuits are analyzed and compared in terms of parameters like DC gain, unity-gain frequency, phase margin, CMRR, power dissipated, slew rate, and input referred noise.\",\"PeriodicalId\":39974,\"journal\":{\"name\":\"Journal of Integrated Circuits and Systems\",\"volume\":\" \",\"pages\":\"\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2021-12-31\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Journal of Integrated Circuits and Systems\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.29292/jics.v16i3.498\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"Q4\",\"JCRName\":\"Engineering\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Journal of Integrated Circuits and Systems","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.29292/jics.v16i3.498","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q4","JCRName":"Engineering","Score":null,"Total":0}
A 0.25-V Three-stage State Feedback Bulk-driven OTA for Wide Range Load Applications
This article employs a nested state feedback compensation technique to a three-stage bulk-driven operational transconductance amplifier (OTA). The projected OTA circuit consists of a bulk-driven PMOS amplifier, gate-driven NMOS amplifier, and common source (CS) amplifier. The entire transistors in the amplifier core are configuredwith self-cascode transistor topology to increase its output impedance. All transistors are designed to operate in a weak inversion in order to dissipate less power. Cross-coupled transistor pair topology in the bulk-driven stage allows to improve the effective transconductance of OTA. The CS amplifier can drive a large load capacitor. The polarities and transconductance gains of feedback blocks are controlled appropriately to obtain the desired DC gain and bandwidth. The capacitor-less compensation strategy allows the fabrication of the OTA using the minimum area. Conventional bulk-driven miler OTA, Bulk-driven stage improved indirect-feedback OTA (BSIF OTA), Gate-driven stage added bulk-driven OTA (GSIF OTA), and proposed bulk-driven OTA topologies are designed and simulated using cadence spectre tool at 25 mV supply voltage in the 65nm CMOS process. These OTA circuits are analyzed and compared in terms of parameters like DC gain, unity-gain frequency, phase margin, CMRR, power dissipated, slew rate, and input referred noise.
期刊介绍:
This journal will present state-of-art papers on Integrated Circuits and Systems. It is an effort of both Brazilian Microelectronics Society - SBMicro and Brazilian Computer Society - SBC to create a new scientific journal covering Process and Materials, Device and Characterization, Design, Test and CAD of Integrated Circuits and Systems. The Journal of Integrated Circuits and Systems is published through Special Issues on subjects to be defined by the Editorial Board. Special issues will publish selected papers from both Brazilian Societies annual conferences, SBCCI - Symposium on Integrated Circuits and Systems and SBMicro - Symposium on Microelectronics Technology and Devices.