International Conference on Design and Test of Integrated Systems in Nanoscale Technology, 2006. DTIS 2006.最新文献_第2页

Design and implementation of an 11-bit non-linear interpolation DAC 一个11位非线性插值DAC的设计与实现

International Conference on Design and Test of Integrated Systems in Nanoscale Technology, 2006. DTIS 2006. Pub Date : 2006-10-16 DOI: 10.1080/00207210701827855

S. Eisa, K. Shehata, H. Ragai

引用次数: 2

An FPGA hardware implementation of the Rijndael block cipher Rijndael分组密码的FPGA硬件实现

International Conference on Design and Test of Integrated Systems in Nanoscale Technology, 2006. DTIS 2006. Pub Date : 2006-10-16 DOI: 10.1109/DTIS.2006.1708717

C. Dhoha, S. Ben Othman, S. Ben Saoud

引用次数: 1

Trends in tests and failure mechanisms in deep sub-micron technologies 深亚微米技术的试验趋势和失效机制

International Conference on Design and Test of Integrated Systems in Nanoscale Technology, 2006. DTIS 2006. Pub Date : 2006-10-16 DOI: 10.1109/DTIS.2006.1708677

S. Hamdioui, Z. Al-Ars, L. Mhamdi, G. Gaydadjiev, S. Vassiliadis

引用次数: 8

Simultaneous delay optimization and depth reduction in logic trees with minimum resources 用最小资源同时优化逻辑树的延迟和深度缩减

International Conference on Design and Test of Integrated Systems in Nanoscale Technology, 2006. DTIS 2006. Pub Date : 2006-10-16 DOI: 10.1109/DTIS.2006.1708714

P. Balasubramanian, P. Prathibh

引用次数: 0

A new synchronization policy between PSL checkers and SystemC designs at transaction level 事务级PSL检查器和SystemC设计之间的新同步策略

International Conference on Design and Test of Integrated Systems in Nanoscale Technology, 2006. DTIS 2006. Pub Date : 2006-10-16 DOI: 10.1109/DTIS.2006.1708698

Younes Lahbib, M. Ghrab, Maher Hechkel, F. Ghenassia, R. Tourki

引用次数: 10

Method for embedded application prototyping based on SoC platform and architecture model 基于SoC平台和体系结构模型的嵌入式应用原型设计方法

International Conference on Design and Test of Integrated Systems in Nanoscale Technology, 2006. DTIS 2006. Pub Date : 2006-10-16 DOI: 10.1109/DTIS.2006.1708689

Y. Aoudnil, G. Gogniat, K. Louki, J. Philippe, M. Abid

引用次数: 0

Magnetic domain wall logic requires new synthesis methodologies 磁畴壁逻辑需要新的综合方法

International Conference on Design and Test of Integrated Systems in Nanoscale Technology, 2006. DTIS 2006. Pub Date : 2006-10-16 DOI: 10.1109/DTIS.2006.1708707

Jacques-Olivier Klein, E. Belhaire, C. Chappert, R. Cowburn, D. Read, D. Petit

引用次数: 4

Analysis of multilayer microstrip filter by wave concept iterative process 用波概念迭代法分析多层微带滤波器

International Conference on Design and Test of Integrated Systems in Nanoscale Technology, 2006. DTIS 2006. Pub Date : 2006-10-16 DOI: 10.1109/DTIS.2006.1708705

E. Hajlaoui, M. Glaoui, H. Trabelsi

{"title":"Analysis of multilayer microstrip filter by wave concept iterative process","authors":"E. Hajlaoui, M. Glaoui, H. Trabelsi","doi":"10.1109/DTIS.2006.1708705","DOIUrl":"https://doi.org/10.1109/DTIS.2006.1708705","url":null,"abstract":"An iterative method based on the concept of waves is presented to determine features of very high frequency's electronic circuits in a planar wave guide. The analysis takes into account eventual coupling parasites. A two dimensional fast Fourier transformation algorithm is introduced to simplify-calculations and accelerate method convergence. The general formulation and the procedure of the iterative method implementation in frequency domain are described. In this article, the authors intend to study a double-layer dielectric substrate. This filter demonstrates the use of the third (vertical) dimension in the design of microstrip devices. The approach involves the mixed magnetic and electric filed equation technique and the wave concept iterative process which involves S-parameters extraction technique based on a simple form of matched toad simulation. In this sense, a program in FORTRAX has been elaborated to determine different parameters Sij characterizing the studied structure. The numerical results are compared to results for microstrip structure and compared to those presented in other references. They show good agreement. The approach is demonstrated in detail for 2-port structures, with an outline of how it can readily be extended to the n-port case","PeriodicalId":399250,"journal":{"name":"International Conference on Design and Test of Integrated Systems in Nanoscale Technology, 2006. DTIS 2006.","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124897792","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Design of enhanced performances CMOS RF mixers suitable for multi-standards receiver 适用于多标准接收机的增强型CMOS射频混频器设计

International Conference on Design and Test of Integrated Systems in Nanoscale Technology, 2006. DTIS 2006. Pub Date : 2006-10-16 DOI: 10.1109/DTIS.2006.1708676

S. Douss, M. Loulou

{"title":"Design of enhanced performances CMOS RF mixers suitable for multi-standards receiver","authors":"S. Douss, M. Loulou","doi":"10.1109/DTIS.2006.1708676","DOIUrl":"https://doi.org/10.1109/DTIS.2006.1708676","url":null,"abstract":"The design of multi-standards CMOS mixers is presented in this paper. The front-end is designed to be operational for three standards at the same time: Global System Mobile (GSM), Digital Enhanced Cordless Telephone systems (DECT) and Universal Mobile Telecommunication System (UMTS). The required specifications for those standards are: a noise figure NF < 10dB, a -1dB compression point CP1 < -10dBm and a conversion gain CG > 15dB for a frequency operation up to 2.5 GHz. Three active mixer's structures are presented. The first is based on the Gilbert cell to which is added an output IF stage, a common mode feedback stage, and an isolation stage between the mixer LO and RF input terminals. This structure presents a good linearity and noise figure, but it produces a low conversion gain. The second structure consists in adding two PMOS transistors with the NMOS RF stage transistors in order to increase conversion gain. In the third structure, the authors replaced PMOS transistors by resistive loads. This work is achieved by a figure of merit development, in order to make possible the mixers topology's comparison. According to the developed figure of merit, folded switching mixer (2nd structure) achieves the best performances. With this topology the following simulation results are: noise figure (NF) 7.98 dB, conversion gain 14.8 dB, linearity (CP1) -4 dBm with a power consumption of 30 mW","PeriodicalId":399250,"journal":{"name":"International Conference on Design and Test of Integrated Systems in Nanoscale Technology, 2006. DTIS 2006.","volume":"61 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122025827","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

A low-power design methodology for single-stage operational amplifiers 一种单级运算放大器的低功耗设计方法

International Conference on Design and Test of Integrated Systems in Nanoscale Technology, 2006. DTIS 2006. Pub Date : 2006-10-16 DOI: 10.1109/DTIS.2006.1708694

H. Aininzadeh, Mohammad Danaie, R. Lotfi

引用次数: 7