{"title":"适用于多标准接收机的增强型CMOS射频混频器设计","authors":"S. Douss, M. Loulou","doi":"10.1109/DTIS.2006.1708676","DOIUrl":null,"url":null,"abstract":"The design of multi-standards CMOS mixers is presented in this paper. The front-end is designed to be operational for three standards at the same time: Global System Mobile (GSM), Digital Enhanced Cordless Telephone systems (DECT) and Universal Mobile Telecommunication System (UMTS). The required specifications for those standards are: a noise figure NF < 10dB, a -1dB compression point CP1 < -10dBm and a conversion gain CG > 15dB for a frequency operation up to 2.5 GHz. Three active mixer's structures are presented. The first is based on the Gilbert cell to which is added an output IF stage, a common mode feedback stage, and an isolation stage between the mixer LO and RF input terminals. This structure presents a good linearity and noise figure, but it produces a low conversion gain. The second structure consists in adding two PMOS transistors with the NMOS RF stage transistors in order to increase conversion gain. In the third structure, the authors replaced PMOS transistors by resistive loads. This work is achieved by a figure of merit development, in order to make possible the mixers topology's comparison. According to the developed figure of merit, folded switching mixer (2nd structure) achieves the best performances. With this topology the following simulation results are: noise figure (NF) 7.98 dB, conversion gain 14.8 dB, linearity (CP1) -4 dBm with a power consumption of 30 mW","PeriodicalId":399250,"journal":{"name":"International Conference on Design and Test of Integrated Systems in Nanoscale Technology, 2006. DTIS 2006.","volume":"61 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2006-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":"{\"title\":\"Design of enhanced performances CMOS RF mixers suitable for multi-standards receiver\",\"authors\":\"S. Douss, M. Loulou\",\"doi\":\"10.1109/DTIS.2006.1708676\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The design of multi-standards CMOS mixers is presented in this paper. The front-end is designed to be operational for three standards at the same time: Global System Mobile (GSM), Digital Enhanced Cordless Telephone systems (DECT) and Universal Mobile Telecommunication System (UMTS). The required specifications for those standards are: a noise figure NF < 10dB, a -1dB compression point CP1 < -10dBm and a conversion gain CG > 15dB for a frequency operation up to 2.5 GHz. Three active mixer's structures are presented. The first is based on the Gilbert cell to which is added an output IF stage, a common mode feedback stage, and an isolation stage between the mixer LO and RF input terminals. This structure presents a good linearity and noise figure, but it produces a low conversion gain. The second structure consists in adding two PMOS transistors with the NMOS RF stage transistors in order to increase conversion gain. In the third structure, the authors replaced PMOS transistors by resistive loads. This work is achieved by a figure of merit development, in order to make possible the mixers topology's comparison. According to the developed figure of merit, folded switching mixer (2nd structure) achieves the best performances. With this topology the following simulation results are: noise figure (NF) 7.98 dB, conversion gain 14.8 dB, linearity (CP1) -4 dBm with a power consumption of 30 mW\",\"PeriodicalId\":399250,\"journal\":{\"name\":\"International Conference on Design and Test of Integrated Systems in Nanoscale Technology, 2006. DTIS 2006.\",\"volume\":\"61 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2006-10-16\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"5\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"International Conference on Design and Test of Integrated Systems in Nanoscale Technology, 2006. DTIS 2006.\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/DTIS.2006.1708676\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"International Conference on Design and Test of Integrated Systems in Nanoscale Technology, 2006. DTIS 2006.","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/DTIS.2006.1708676","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Design of enhanced performances CMOS RF mixers suitable for multi-standards receiver
The design of multi-standards CMOS mixers is presented in this paper. The front-end is designed to be operational for three standards at the same time: Global System Mobile (GSM), Digital Enhanced Cordless Telephone systems (DECT) and Universal Mobile Telecommunication System (UMTS). The required specifications for those standards are: a noise figure NF < 10dB, a -1dB compression point CP1 < -10dBm and a conversion gain CG > 15dB for a frequency operation up to 2.5 GHz. Three active mixer's structures are presented. The first is based on the Gilbert cell to which is added an output IF stage, a common mode feedback stage, and an isolation stage between the mixer LO and RF input terminals. This structure presents a good linearity and noise figure, but it produces a low conversion gain. The second structure consists in adding two PMOS transistors with the NMOS RF stage transistors in order to increase conversion gain. In the third structure, the authors replaced PMOS transistors by resistive loads. This work is achieved by a figure of merit development, in order to make possible the mixers topology's comparison. According to the developed figure of merit, folded switching mixer (2nd structure) achieves the best performances. With this topology the following simulation results are: noise figure (NF) 7.98 dB, conversion gain 14.8 dB, linearity (CP1) -4 dBm with a power consumption of 30 mW