2016 IEEE Asian Hardware-Oriented Security and Trust (AsianHOST)最新文献

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Comparing Sboxes of ciphers from the perspective of side-channel attacks 从旁信道攻击的角度比较两种密码
2016 IEEE Asian Hardware-Oriented Security and Trust (AsianHOST) Pub Date : 2016-12-19 DOI: 10.1109/AsianHOST.2016.7835556
Liran Lerman, O. Markowitch, Nikita Veshchikov
{"title":"Comparing Sboxes of ciphers from the perspective of side-channel attacks","authors":"Liran Lerman, O. Markowitch, Nikita Veshchikov","doi":"10.1109/AsianHOST.2016.7835556","DOIUrl":"https://doi.org/10.1109/AsianHOST.2016.7835556","url":null,"abstract":"Side-channel attacks exploit physical characteristics of implementations of cryptographic algorithms in order to extract sensitive information such as the secret key. These physical attacks are among the most powerful attacks against real-world crypto-systems. This paper analyses the non-linear part (called Sboxes) of ciphers, which is often targeted by implementation attacks. We analyse Sboxes of several candidates that were submitted to the competition on authenticated encryption (CAESAR) as well as several other ciphers. We compare theoretical metrics with results from simulations and with real experiments. In this paper, we demonstrate that, in some contexts, the theoretical metrics provide no information on the resiliency of the Sboxes against side-channel attacks.","PeriodicalId":394462,"journal":{"name":"2016 IEEE Asian Hardware-Oriented Security and Trust (AsianHOST)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131027863","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
An ultra-low overhead LUT-based PUF for FPGA 一种用于FPGA的超低开销lut PUF
2016 IEEE Asian Hardware-Oriented Security and Trust (AsianHOST) Pub Date : 2016-12-01 DOI: 10.1109/AsianHOST.2016.7835554
Jiadong Wang, Aijiao Cui, Mengyang Li, G. Qu, Huawei Li
{"title":"An ultra-low overhead LUT-based PUF for FPGA","authors":"Jiadong Wang, Aijiao Cui, Mengyang Li, G. Qu, Huawei Li","doi":"10.1109/AsianHOST.2016.7835554","DOIUrl":"https://doi.org/10.1109/AsianHOST.2016.7835554","url":null,"abstract":"Physical unclonable function (PUF) utilizes the unexpected intrinsic manufacturing process variations of device to generate unique bit streams for authentication, key generation and random number generation. It has emerged as a promising primitive to address various challenges in hardware security. Traditional PUF schemes, such as arbiter PUF and ring oscillator (RO) PUF, do not have efficient implementations on FPGA and thus limit their usage as FPGA becomes the dominate design platform for today's emerging applications. In this paper, we propose a novel look-up table (LUT) shift register (SR) based PUF scheme for FPGA. This PUF incurs ultra1-low resource overhead, only two SLICEs to produce a 128-bit signature in our experimentation on XILINX Virtex-5 FPGA. Meanwhile, the PUF response are good in terms of uniqueness and robustness. At the same temperature, the proposed PUF has a 99%+ reliability on its response. When temperature changes between 25°C and 75°C, the robustness drops, but is still over 90%.","PeriodicalId":394462,"journal":{"name":"2016 IEEE Asian Hardware-Oriented Security and Trust (AsianHOST)","volume":"18 4","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120925179","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Enhancing noise sensitivity of embedded SRAMs for robust true random number generation in SoCs 提高嵌入式ram的噪声敏感性,实现soc中真随机数的鲁棒生成
2016 IEEE Asian Hardware-Oriented Security and Trust (AsianHOST) Pub Date : 2016-12-01 DOI: 10.1109/AsianHOST.2016.7835559
Md. Tauhidur Rahman, Domenic Forte, Xiaoxiao Wang, M. Tehranipoor
{"title":"Enhancing noise sensitivity of embedded SRAMs for robust true random number generation in SoCs","authors":"Md. Tauhidur Rahman, Domenic Forte, Xiaoxiao Wang, M. Tehranipoor","doi":"10.1109/AsianHOST.2016.7835559","DOIUrl":"https://doi.org/10.1109/AsianHOST.2016.7835559","url":null,"abstract":"True random number generators (TRNGs) play an important role in trusted execution and communication for modern system on chips (SoCs). Building a TRNG in today's SoCs is complex and often challenging because it must have uniform statistical characteristics at any operating condition and workload, and in hostile environments over the entire system lifetime. The startup outputs of SRAM cells, another vital component in SoCs, have been used to generate random numbers and/or unique keys. However, the quality of existing SRAM-based TRNGs is limited due to limited amount of entropy which also can be manipulated by operating voltage or temperature. Another disadvantage of the existing SRAM-based TRNG is that the system requires power off and on to obtain random numbers which hampers the system performance. In this paper, we propose a noise sensitive embedded SRAM (NS-SRAM) based TRNG that reliably provides unpredictable random numbers at high rates regardless of the operating conditions. We design a noise sensitive SRAM and propose a technique that utilizes the existing power-management scheme to obtain random numbers. We evaluate the quality of NS-SRAM based TRNGs for 90nm, 45nm, and 32nm technology nodes. The proposed NS-SRAM based TRnG is ∼ 275X faster and ∼ 432X more area efficient (excluding post-processing overhead) than existing SRAM-based TRNGs.","PeriodicalId":394462,"journal":{"name":"2016 IEEE Asian Hardware-Oriented Security and Trust (AsianHOST)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125034003","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
On-chip substrate-bounce monitoring for laser-fault countermeasure 用于激光故障对抗的片上衬底弹跳监测
2016 IEEE Asian Hardware-Oriented Security and Trust (AsianHOST) Pub Date : 2016-12-01 DOI: 10.1109/AsianHOST.2016.7835565
Kohei Matsuda, N. Miura, M. Nagata, Yu-ichi Hayashi, Tatsuya Fujii, K. Sakiyama
{"title":"On-chip substrate-bounce monitoring for laser-fault countermeasure","authors":"Kohei Matsuda, N. Miura, M. Nagata, Yu-ichi Hayashi, Tatsuya Fujii, K. Sakiyama","doi":"10.1109/AsianHOST.2016.7835565","DOIUrl":"https://doi.org/10.1109/AsianHOST.2016.7835565","url":null,"abstract":"This paper presents a reactive sensor-based IC countermeasure against a laser-fault injection attack on a cryptographic processor. IC substrate potential bounce due to laser injection is in-situ monitored by distributed 1bit compact comparators to raise the alarm against the attack. Since the laser power to induce fault is very high, the associated substrate bounce is large and wide-spread over a broad chip area. The efficient attack detection is thus possible with small hardware overhead. To further squeeze the overhead, an optimal sensor design methodology is proposed. An in-situ precise measurement of the bounce by utilizing an on-chip monitor successfully pre-characterizes the magnitude of the critical substrate bounce causing fault injection. The sensor sensitivity, position, and pitch could be optimized accordingly. A test chip is designed and fabricated in 0.18µm CMOS to evaluate the efficiency and validity of the proposed countermeasure.","PeriodicalId":394462,"journal":{"name":"2016 IEEE Asian Hardware-Oriented Security and Trust (AsianHOST)","volume":"628 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114837231","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
Sneak path enabled authentication for memristive crossbar memories 为记忆交叉栏内存启用了偷偷路径认证
2016 IEEE Asian Hardware-Oriented Security and Trust (AsianHOST) Pub Date : 2016-12-01 DOI: 10.1109/ASIANHOST.2016.7835568
M. Majumder, Mesbah Uddin, G. Rose, Jeyavijayan Rajendran
{"title":"Sneak path enabled authentication for memristive crossbar memories","authors":"M. Majumder, Mesbah Uddin, G. Rose, Jeyavijayan Rajendran","doi":"10.1109/ASIANHOST.2016.7835568","DOIUrl":"https://doi.org/10.1109/ASIANHOST.2016.7835568","url":null,"abstract":"The memristive crossbar has emerged as a promising candidate for future memory technologies. In this paper, we explore a sneak path enabled authentication method for memristive crossbar memory. We show that, due to data dependent sneak paths currents, memristive crossbar memory can inherently produce authenticating tags for stored data. A reserved row of memory cells is also used in the proposed protocol which is reconfigured randomly during every write to the memory. We perform a numerical probabilistic analysis for evaluating the security of the proposed protocol for different sizes of crossbar and generated tags. Security is measured in terms of minimum number of trials needed to get a collision among data tags. Simulation results can be extrapolated for predicting the security of the system with larger data tags. Since the memory itself with minimal additional circuitry is used as the tag generating function, the proposed protocol exhibits low overhead compared to more conventional methods.","PeriodicalId":394462,"journal":{"name":"2016 IEEE Asian Hardware-Oriented Security and Trust (AsianHOST)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125503359","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
RECORD: Temporarily Randomized Encoding of COmbinational Logic for Resistance to Data Leakage from hardware Trojan 组合逻辑的临时随机编码,以抵抗硬件木马的数据泄漏
2016 IEEE Asian Hardware-Oriented Security and Trust (AsianHOST) Pub Date : 2016-12-01 DOI: 10.1109/AsianHOST.2016.7835566
Travis E. Schulze, K. Kwiat, C. Kamhoua, Shih-Chieh Chang, Yiyu Shi
{"title":"RECORD: Temporarily Randomized Encoding of COmbinational Logic for Resistance to Data Leakage from hardware Trojan","authors":"Travis E. Schulze, K. Kwiat, C. Kamhoua, Shih-Chieh Chang, Yiyu Shi","doi":"10.1109/AsianHOST.2016.7835566","DOIUrl":"https://doi.org/10.1109/AsianHOST.2016.7835566","url":null,"abstract":"Many design companies have gone fabless and rely on external fabrication facilities to produce chips due to increasing cost of semiconductor manufacturing. However, not all of these facilities can be considered trustworthy; some may inject hardware Trojans and jeopardize the security of the system. One common objective of hardware Trojans is to a establish side channel for data leakage. While extensive literature exists on various defensive measures, almost all of them focus on preventing the establishment of side channels, and can be compromised if attackers gain access to the physical chip and can perform reverse engineering between multiple fabrication runs. In this paper, we propose RECORD: Temporarily Randomized Encoding of COmbinational Logic for Resistance to Data Leakage. RECORD a novel scheme of temporarily randomized encoding for combinational logic that, with the aid of Quilt Packaging, aims to prevent attackers from interpreting the data. Experimental results on a 45 nm 8-bit Advanced Encryption Standard (AES) Substitution Box (Sbox) showed that RECORD can effectively hide information with 2.3× area overhead, 2.77× dynamic power increase and negligible delay overhead.","PeriodicalId":394462,"journal":{"name":"2016 IEEE Asian Hardware-Oriented Security and Trust (AsianHOST)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133269063","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Laser irradiation on EEPROM sense amplifiers enhances side-channel leakage of read bits 激光照射EEPROM感测放大器增强读位侧漏
2016 IEEE Asian Hardware-Oriented Security and Trust (AsianHOST) Pub Date : 2016-12-01 DOI: 10.1109/AsianHOST.2016.7835564
Junichi Sakamoto, Daisuke Fujimoto, Tsutomu Matsumoto
{"title":"Laser irradiation on EEPROM sense amplifiers enhances side-channel leakage of read bits","authors":"Junichi Sakamoto, Daisuke Fujimoto, Tsutomu Matsumoto","doi":"10.1109/AsianHOST.2016.7835564","DOIUrl":"https://doi.org/10.1109/AsianHOST.2016.7835564","url":null,"abstract":"Side-channel attacks that compromise confidentiality of memory contents have become a major concern for device manufacturers and users. Electrically erasable programmable read-only memory (EEPROM) implemented on embedded devices contains several types of sensitive information, and it shall strictly prohibit unauthorized access to such information. This paper introduces a new technique that extracts data while reading from EEPROM using a combination of power analysis and laser irradiation techniques. One characteristic of the proposed method is that it uses laser irradiation onto a sense amplifier in a manner that enables it to obtain multiple bits for each irradiation position. This also implies that we can obtain sensitive information from memory content selectively, as the proposed method extracts the read bits via a sense amplifier (values while reading in real time) rather than states of memory cell. Another characteristic of this method is that the laser injects no logical errors onto the target devices. Because the proposed method uses laser induced current, conventional software countermeasures against fault-based attacks are ineffective against it. To demonstrate the effectiveness of the proposed method, this paper exhibits a data extraction experiment recovering the complete contents of a test program stored in the flash EEPROM contained in an ATMega 8515 microcontroller.","PeriodicalId":394462,"journal":{"name":"2016 IEEE Asian Hardware-Oriented Security and Trust (AsianHOST)","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134224079","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
RPUF: Physical Unclonable Function with Randomized Challenge to resist modeling attack RPUF:抗建模攻击的随机挑战物理不可克隆函数
2016 IEEE Asian Hardware-Oriented Security and Trust (AsianHOST) Pub Date : 2016-12-01 DOI: 10.1109/AsianHOST.2016.7835567
Jing Ye, Yu Hu, Xiaowei Li
{"title":"RPUF: Physical Unclonable Function with Randomized Challenge to resist modeling attack","authors":"Jing Ye, Yu Hu, Xiaowei Li","doi":"10.1109/AsianHOST.2016.7835567","DOIUrl":"https://doi.org/10.1109/AsianHOST.2016.7835567","url":null,"abstract":"The Physical Unclonable Function (PUF) has broad application prospects in the field of hardware security. The strong PUFs with numerous Challenge-Response Pairs (CRPs), such as various arbiter PUFs, mirror current PUF, and voltage transfer PUF, are severely threatened by the machine learning based modeling attacks. To handle this issue, we propose the Physical Unclonable Function with Randomized challenge (RPUF). Challenges are randomized by a Random Number Generator (RNG) before inputting to the strong PUF, so to prevent attackers from collecting effective training set for conducting modeling attacks. Experiments on both simulations and FPGAs prove the effectiveness of RPUF in resisting modeling attack, with negligible effects on uniformity, uniqueness, and reliability.","PeriodicalId":394462,"journal":{"name":"2016 IEEE Asian Hardware-Oriented Security and Trust (AsianHOST)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134251441","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 44
Test generation for combinational hardware Trojans 组合硬件木马的测试生成
2016 IEEE Asian Hardware-Oriented Security and Trust (AsianHOST) Pub Date : 2016-12-01 DOI: 10.1109/AsianHOST.2016.7835569
Sying-Jyan Wang, J. Wei, Shih-Heng Huang, Katherine Shu-Min Li
{"title":"Test generation for combinational hardware Trojans","authors":"Sying-Jyan Wang, J. Wei, Shih-Heng Huang, Katherine Shu-Min Li","doi":"10.1109/AsianHOST.2016.7835569","DOIUrl":"https://doi.org/10.1109/AsianHOST.2016.7835569","url":null,"abstract":"Hardware Trojans become a security threat to the integrated circuit supply chain. Detecting hardware Trojans is difficult as such circuits are stealthy in nature and triggered only under rare conditions. Traditional ATPG patterns are not useful for Trojan activation, and in general random patterns have to be applied for Trojan detection. In this paper we will first analyze how combinational rare conditions can be constructed in a systemic way, so that a Trojan circuit with a desired triggering probability can be synthesized accordingly. A watch list of Trojan candidates can be constructed according to the analysis. A set of test cubes can be generated from the candidates, and experimental results that the number of test cubes is restricted in most cases. The number of test vectors can be further reduced when physical layout information is taken into account. In addition, we can augment the test cubes with random assignment of X-bits to deal with addition trigger signals other than the target events. The results of this study should be helpful to the development of Trojan detection methods.","PeriodicalId":394462,"journal":{"name":"2016 IEEE Asian Hardware-Oriented Security and Trust (AsianHOST)","volume":"62 9","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114042075","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
A new approach for root-causing attacks on digital microfluidic devices 一种针对数字微流控装置的根源攻击新方法
2016 IEEE Asian Hardware-Oriented Security and Trust (AsianHOST) Pub Date : 2016-12-01 DOI: 10.1109/AsianHOST.2016.7835550
Pushpita Roy, A. Banerjee
{"title":"A new approach for root-causing attacks on digital microfluidic devices","authors":"Pushpita Roy, A. Banerjee","doi":"10.1109/AsianHOST.2016.7835550","DOIUrl":"https://doi.org/10.1109/AsianHOST.2016.7835550","url":null,"abstract":"Recent research on security aspects of digital microfluidic biochips (DMFBs) has revealed several alarming backdoors in the established DMFB design flow that can lead to unacceptable compromises in assay results, often leading to catastrophic consequences. This has led to a growing concern about vulnerability issues of DMFBs and assay manipulation attacks that are used for clinical diagnostics in healthcare. In this paper, we propose a novel scheme for localization and root-causing of assay manipulation attacks. Our approach takes as input a golden implementation of an assay and the attacker modified one, and uses symbolic reasoning on the actuation sequences of the golden assay and the compromised one to derive possible operations that may have been compromised in the modified assay. Additionally, our method can utilize intermediate checkpoint observations to derive more precise attack locations. Experimental results show the efficacy of our proposal.","PeriodicalId":394462,"journal":{"name":"2016 IEEE Asian Hardware-Oriented Security and Trust (AsianHOST)","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121494034","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 16
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