Test generation for combinational hardware Trojans

Abstract

Hardware Trojans become a security threat to the integrated circuit supply chain. Detecting hardware Trojans is difficult as such circuits are stealthy in nature and triggered only under rare conditions. Traditional ATPG patterns are not useful for Trojan activation, and in general random patterns have to be applied for Trojan detection. In this paper we will first analyze how combinational rare conditions can be constructed in a systemic way, so that a Trojan circuit with a desired triggering probability can be synthesized accordingly. A watch list of Trojan candidates can be constructed according to the analysis. A set of test cubes can be generated from the candidates, and experimental results that the number of test cubes is restricted in most cases. The number of test vectors can be further reduced when physical layout information is taken into account. In addition, we can augment the test cubes with random assignment of X-bits to deal with addition trigger signals other than the target events. The results of this study should be helpful to the development of Trojan detection methods.