{"title":"Chosen ciphertext Simple Power Analysis on software 8-bit implementation of ring-LWE encryption","authors":"Aesun Park, Dong‐Guk Han","doi":"10.1109/AsianHOST.2016.7835555","DOIUrl":"https://doi.org/10.1109/AsianHOST.2016.7835555","url":null,"abstract":"Post-quantum cryptographic schemes have been developed in response to the rise of quantum computers. Fortunately, several schemes have been developed with quantum resistance. However, it is not surprising that implementations of post-quantum cryptographic schemes are vulnerable to Side Channel Analysis (SCA) attacks because post-quantum cryptographic schemes will require implementation on the same platforms which are widely used in the industrial field. SCA attack method and their countermeasures for code-based post-quantum cryptosystem, such as McEliece, have been investigated. Unfortunately, the investigation of the ring-LWE problem in terms of SCA is as yet insufficient. There has only been limited research on the side-channel vulnerabilities of lattice-based implementations. In this paper, we propose the first Simple Power Analysis (SPA) attack on the ring-LWE encryption scheme. The proposed attack exploits the chosen ciphertext and the vulnerability associated with the modular addition, which is applicable when a ring-LWE encryption scheme operates on 8-bit microcontroller devices. We also identify the vulnerability associated with the modular addition operation of 8-bit implementation. When operating a ring-LWE encryption scheme on an 8-bit device, the secret key can be revealed via this vulnerability using the proposed chosen-ciphertext SPA attack.","PeriodicalId":394462,"journal":{"name":"2016 IEEE Asian Hardware-Oriented Security and Trust (AsianHOST)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130636226","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"An enhanced classification-based golden chips-free hardware Trojan detection technique","authors":"Mingfu Xue, Jian Wang, A. Hu","doi":"10.1109/AsianHOST.2016.7835553","DOIUrl":"https://doi.org/10.1109/AsianHOST.2016.7835553","url":null,"abstract":"Recently, integrated circuits (ICs) are becoming increasing vulnerable to hardware Trojans. Most of existing works require golden chips to provide references for hardware Trojan detection. However, obtaining a golden chip is extremely difficult or even not exists. This paper presents a novel automated hardware Trojan detection technique based on enhanced two-class classification while eliminating the need of golden chips after fabrication. We formulate the Trojan detection problem into a classification problem, and train the algorithms using simulated ICs during IC design flow. The algorithm will form a classifier which can automatically identify Trojan-free and Trojan-inserted ICs during test-time. Moreover, we propose several optional optimized methods to enhance the technique: 1) we propose adaptive iterative optimization of one algorithm by focusing on errors, in which the weight-adjusting are based on how successful the algorithm was in the previous iteration; 2) we analyze the misclassified ICs' numbers of certain algorithms and present the matched algorithm-pairs; 3) we alter the algorithms to take into account of the costs of making different detection decisions, called cost-sensitive detection; 4) we present the suitable algorithm settings against high level of process variations. Experiment results on benchmark circuits show that the proposed technique can detect both known Trojans and various unknown Trojans with high accuracy and recall (90%∼100%). Since we didn't add any extra circuit to the design, there is no overhead of this approach.","PeriodicalId":394462,"journal":{"name":"2016 IEEE Asian Hardware-Oriented Security and Trust (AsianHOST)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116017826","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Jaya Dofe, Chen Yan, Scott Kontak, E. Salman, Qiaoyan Yu
{"title":"Transistor-level camouflaged logic locking method for monolithic 3D IC security","authors":"Jaya Dofe, Chen Yan, Scott Kontak, E. Salman, Qiaoyan Yu","doi":"10.1109/AsianHOST.2016.7835570","DOIUrl":"https://doi.org/10.1109/AsianHOST.2016.7835570","url":null,"abstract":"This work proposes a novel method for transistor-level logic locking to address intellectual property (IP) piracy and reverse engineering attacks in monolithic three-dimensional (M3D) ICs. The proposed method locks logic gates by independently inserting parallel or serial locking transistors and camouflaged contacts in multiple tiers in M3D ICs. Without the correct key bits and confidential information for camouflaged contacts, the locked logic gates will malfunction and significantly alter power profiles, which makes reverse engineering attacks more difficult. The performance overhead of the proposed method is evaluated with ISCAS'85 benchmark circuits synthesized and placed with a customized M3D IC library. Case study on c6288 benchmark circuit shows that the proposed locking method with the correct key increases the power by only 0.26%. On average, this method consumes 2.3% more transistors than the baseline ISCAS'85 benchmark circuits.","PeriodicalId":394462,"journal":{"name":"2016 IEEE Asian Hardware-Oriented Security and Trust (AsianHOST)","volume":"124 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123199377","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Using image sensor PUF as root of trust for birthmarking of perceptual image hash","authors":"Yuan Cao, Le Zhang, Chip-Hong Chang","doi":"10.1109/AsianHOST.2016.7835573","DOIUrl":"https://doi.org/10.1109/AsianHOST.2016.7835573","url":null,"abstract":"The perceptual image hash has been widely used for integrity check of digital image content. Existing image hashes fail to identify the origin of image acquisition and non-repudiable authentication is contingent on the privacy of secret key. This paper presents a new and more secure image hashing scheme by exploiting the CMOS image sensor physical unclonable function (PUF) as a root of trust to imprint a birthmark into the image hash. The hash vector is generated directly by the CMOS image sensor based on the content-based features extracted from its captured image and the timestamp of the image without the need for a shared secret key for its authentication. Other than the ability to detect malicious tampering of image content from normal benign image processing operations, the use of CMOS image sensor PUF as a random one-way function to map the extracted feature and the timestamp to a hash vector provides a non-repudiable proof of the original image acquisition device and time of offence when the digital image content is to be presented as an evidence of a crime. As the hash vector can only be generated by the image sensor when it is powered on, it is inherently secure against invasive, data remanence and replay attacks, which are common threats to key-based perceptual image hashes. Our preliminary experimental results on 49 content-preserving and 5 wilfully tampered copies of an original image captured by a 64 × 64 image sensor PUF fabricated in 180 nm 3.3 V CMOS technology have demonstrated that the tampered images and their regions of alteration can be successfully detected from the hash vectors.","PeriodicalId":394462,"journal":{"name":"2016 IEEE Asian Hardware-Oriented Security and Trust (AsianHOST)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129630585","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Defeating drone jamming with hardware sandboxing","authors":"J. Mead, C. Bobda, Taylor J. L. Whitaker","doi":"10.1109/AsianHOST.2016.7835557","DOIUrl":"https://doi.org/10.1109/AsianHOST.2016.7835557","url":null,"abstract":"In this work, we concern ourselves with the security of drone systems under jamming-based attacks. The focus is on design and synthesis structure with the anti-jamming security needs of drone systems. We explore a relatively new concept known as hardware sandboxing, to provide runtime monitoring of boundary signals and isolation through resource virtualization for non-trusted system-on-chip (SoC) components. We utilize Field Programmable Gate Array (FPGA) based development and target embedded Linux for our drone hardware/software system containing the hardware sandbox. We design and implement our working concept on the Digilent Zybo FPGA, which uses the Xilinx Zynq system. Our design is validated via simulation-based tests to mimic jamming attacks and standalone, stationary tests with commercial transmitter and receiver equipment. In both cases, we are successful in detecting and isolating unwanted behavior.","PeriodicalId":394462,"journal":{"name":"2016 IEEE Asian Hardware-Oriented Security and Trust (AsianHOST)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116871610","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Key extraction from the primary side of a switched-mode power supply","authors":"S. Saab, A. Leiserson, Michael Tunstall","doi":"10.1109/AsianHOST.2016.7835563","DOIUrl":"https://doi.org/10.1109/AsianHOST.2016.7835563","url":null,"abstract":"In this paper we detail techniques that can be used to analyze and attack an AES implementation on an FPGA from the primary (i.e., external) side of a switched-mode power supply. Our attack only requires measurements of the duty cycle of the power supply, and then increases the signal-to-noise ratio (SNR) though averaging, deconvolution and wavelet based detrending. The result is an exploitable source of leakage that allows a secret key to be determined from low-frequency power measurements. The techniques and procedures provide a general approach to performing differential power analysis (DPA) from a single point of information for any single hypothesized intermediate value, suggesting their potential for improving other types of side-channel analysis.","PeriodicalId":394462,"journal":{"name":"2016 IEEE Asian Hardware-Oriented Security and Trust (AsianHOST)","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126984567","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Mehran Mozaffari Kermani, R. Azarderakhsh, Jiafeng Xie
{"title":"Error detection reliable architectures of Camellia block cipher applicable to different variants of its substitution boxes","authors":"Mehran Mozaffari Kermani, R. Azarderakhsh, Jiafeng Xie","doi":"10.1109/AsianHOST.2016.7835560","DOIUrl":"https://doi.org/10.1109/AsianHOST.2016.7835560","url":null,"abstract":"Different security properties are provided by cryptographic architectures to protect sensitive usage models such as implantable and wearable medical devices and nano-sensor nodes. Nevertheless, the way such algorithms are implemented could undermine the needed security and reliability aims. Unless the reliability of architectures is guaranteed, natural or malicious faults can undermine such objectives. Noting this, in this paper, we present error detection approaches for the Camellia block cipher taking into account its linear and non-linear sub-blocks. We also tailor the presented error detection architectures towards the desirability of using different variants of the S-boxes based on the security and reliability objectives. The merit of the proposed approaches is that (a) they can be tailored and applied to look-up table-based and composite field-based S-boxes, (b) their reliability vs. overhead can be fine-tuned based on the usage models, and (c) they result in high error coverage and acceptable overheads for performance and implementation metrics. We present the results of error simulations and application-specific integrated circuit (ASIC) implementations to benchmark the efficiency of the presented schemes.","PeriodicalId":394462,"journal":{"name":"2016 IEEE Asian Hardware-Oriented Security and Trust (AsianHOST)","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131103436","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Aging attacks for key extraction on permutation-based obfuscation","authors":"Zimu Guo, M. Tehranipoor, Domenic Forte","doi":"10.1109/AsianHOST.2016.7835552","DOIUrl":"https://doi.org/10.1109/AsianHOST.2016.7835552","url":null,"abstract":"Permutation-based obfuscation has been exploited to protect hardware against cloning, overproduction, and reverse engineering with a secret key. In order to prevent key extraction from memory, this key is usually stored in volatile memory. Since the key is erased after the system loses power, this scheme is often considered the best way to prevent a key from being stolen since many attacks would require power. However, in this paper, we propose a new attack where the key is determined by exploring path aging within the permutation network used for obfuscation. Both the theoretical analysis and experimental results are provided. A practical procedure to achieve the proposed attack is also discussed in the context of an attacker's capabilities and knowledge. We also present an adjustment scheme to improve the accuracy of the attack. Various aging durations, process variations and measurement conditions are considered in our simulations. The experimental results show the accuracy of identifying the key is as high as 92.4% and more than enough to reduce the number of brute force combinations required by an attacker.","PeriodicalId":394462,"journal":{"name":"2016 IEEE Asian Hardware-Oriented Security and Trust (AsianHOST)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131101519","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Translating circuit behavior manifestations of hardware Trojans using model checkers into run-time Trojan detection monitors","authors":"S. R. Hasan, C. Kamhoua, K. Kwiat, L. Njilla","doi":"10.1109/AsianHOST.2016.7835571","DOIUrl":"https://doi.org/10.1109/AsianHOST.2016.7835571","url":null,"abstract":"It is a consensus among the researchers, although not proven, that it is close to impossible to guarantee completely secure hardware design. Therefore, it is desired to have run-time hardware Trojan detection techniques. This paper is toward developing a framework of how to achieve run-time hardware Trojan detection units. Although it is difficult to predict the stage of circuit design at which hardware intruder would insert Trojan as well as the hardware Trojan detection methodology that should be applied, behavior patterns of certain design units in the hardware can indicate malicious activities in the design. We propose to translate such behavior patterns using formal verification approaches to establish run-time hardware Trojan detection technique leading which can improve the resiliency of hardware designs against hardware Trojan. We examine the possibility of malicious intrusions in both combinational and sequential circuits that may result in functional incorrectness, and applied our methodology in two example circuits.","PeriodicalId":394462,"journal":{"name":"2016 IEEE Asian Hardware-Oriented Security and Trust (AsianHOST)","volume":"66 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121682079","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"How secure is split manufacturing in preventing hardware trojan?","authors":"Z. Chen, Pingqiang Zhou, Tsung-Yi Ho, Yier Jin","doi":"10.1145/3378163","DOIUrl":"https://doi.org/10.1145/3378163","url":null,"abstract":"With the trend of outsourcing fabrication, split manufacturing is regarded as a promising way to both provide the high-end nodes in untrusted external foundries and protect the design from potential attackers. However, in this work, we show that split manufacturing is not inherently secure. A hardware trojan attacker can still discover necessary information with a simulated annealing based attack approach at the placement level. We further propose a defense approach by moving the insecure gates away from their easily-attacked candidate locations. Experimental results on benchmark circuits show the effectiveness of our proposed methods.","PeriodicalId":394462,"journal":{"name":"2016 IEEE Asian Hardware-Oriented Security and Trust (AsianHOST)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114076588","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}