Enhancing noise sensitivity of embedded SRAMs for robust true random number generation in SoCs

Abstract

True random number generators (TRNGs) play an important role in trusted execution and communication for modern system on chips (SoCs). Building a TRNG in today's SoCs is complex and often challenging because it must have uniform statistical characteristics at any operating condition and workload, and in hostile environments over the entire system lifetime. The startup outputs of SRAM cells, another vital component in SoCs, have been used to generate random numbers and/or unique keys. However, the quality of existing SRAM-based TRNGs is limited due to limited amount of entropy which also can be manipulated by operating voltage or temperature. Another disadvantage of the existing SRAM-based TRNG is that the system requires power off and on to obtain random numbers which hampers the system performance. In this paper, we propose a noise sensitive embedded SRAM (NS-SRAM) based TRNG that reliably provides unpredictable random numbers at high rates regardless of the operating conditions. We design a noise sensitive SRAM and propose a technique that utilizes the existing power-management scheme to obtain random numbers. We evaluate the quality of NS-SRAM based TRNGs for 90nm, 45nm, and 32nm technology nodes. The proposed NS-SRAM based TRnG is ∼ 275X faster and ∼ 432X more area efficient (excluding post-processing overhead) than existing SRAM-based TRNGs.