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2017 IEEE 47th International Symposium on Multiple-Valued Logic (ISMVL)最新文献

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Fast Computation of the Discrete Pascal Transform 离散帕斯卡变换的快速计算
2017 IEEE 47th International Symposium on Multiple-Valued Logic (ISMVL) Pub Date : 2017-05-01 DOI: 10.1109/ISMVL.2017.32
Dušan B. Gajić, R. Stankovic
{"title":"Fast Computation of the Discrete Pascal Transform","authors":"Dušan B. Gajić, R. Stankovic","doi":"10.1109/ISMVL.2017.32","DOIUrl":"https://doi.org/10.1109/ISMVL.2017.32","url":null,"abstract":"The discrete Pascal transform (DPT) is a relatively recently introduced spectral transform based on the concept of the Pascal triangle which has been known for centuries. It is used in digital image processing, digital filtering, pattern recognition, watermarking, and related areas. Its applicabilityis limited by the O(N^2) asymptotical time complexity of bestcurrent algorithms for its computation, where N is the size of the function to be processed. In this paper, we propose a method for the efficient computation of the DPT in O(N logN) time, based on the factorization of its transform matrix into a product of three matrices with special structure - two diagonal matrices and a Toeplitz matrix. The Toeplitz matrix is further embedded into a circulant matrix of order 2N. The diagonalization of the circulant matrix by the Fourier matrix permits the use of the fast Fourier transform (FFT) for performing the computations, leading to an algorithm with the overall computational complexity of O(N logN). Since the entries in the Toeplitz matrix have very different magnitudes, the numerical stability of this algorithm is also discussed. We also consider the issues in implementing the proposed algorithm for highly-parallel computation on graphicsprocessing units (GPUs). The experiments show that computing the DPT using the proposed algorithm processed on GPUs is orders of magnitude faster than the best current approach. As a result, the proposed method can significantly extend the practical applicability of the discrete Pascal transform.","PeriodicalId":393724,"journal":{"name":"2017 IEEE 47th International Symposium on Multiple-Valued Logic (ISMVL)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129960900","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
An Exact Optimization Algorithm for Linear Decomposition of Index Generation Functions 索引生成函数线性分解的精确优化算法
2017 IEEE 47th International Symposium on Multiple-Valued Logic (ISMVL) Pub Date : 2017-05-01 DOI: 10.1109/ISMVL.2017.56
Shinobu Nagayama, Tsutomu Sasao, J. T. Butler
{"title":"An Exact Optimization Algorithm for Linear Decomposition of Index Generation Functions","authors":"Shinobu Nagayama, Tsutomu Sasao, J. T. Butler","doi":"10.1109/ISMVL.2017.56","DOIUrl":"https://doi.org/10.1109/ISMVL.2017.56","url":null,"abstract":"This paper proposes an exact optimization algorithm based on a branch and bound method for linear decomposition of index generation functions. The proposed algorithm efficiently finds the optimum linear decomposition of an index generation function by pruning non-optimum solutions using effective branch and bound strategies. The branch strategy is based on our previous heuristic [2] using a balanced decision tree, and the bound is based on a lower bound on the number of variables needed for linear decomposition. Experimental results using a benchmark index generation function show its optimum linear decompositions and effectiveness of the strategies.","PeriodicalId":393724,"journal":{"name":"2017 IEEE 47th International Symposium on Multiple-Valued Logic (ISMVL)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130785011","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Centralizing Monoids and the Arity of Witnesses 集中独偶群和目击者的数量
2017 IEEE 47th International Symposium on Multiple-Valued Logic (ISMVL) Pub Date : 2017-05-01 DOI: 10.1109/ISMVL.2017.34
Hajime Machida, I. Rosenberg
{"title":"Centralizing Monoids and the Arity of Witnesses","authors":"Hajime Machida, I. Rosenberg","doi":"10.1109/ISMVL.2017.34","DOIUrl":"https://doi.org/10.1109/ISMVL.2017.34","url":null,"abstract":"Multi-variable functions defined over a fixed finite set A are considered. A centralizing monoid M is a set of unary functions on A which commute with all members of some set F of functions on A. The set F is called a witness of M. We show that every centralizing monoid has a witness whose arity does not exceed |A|. Next, we present examples of centralizing monoids on a three-element set which have witnesses of arity 3 but do not have witnesses of arity 2.","PeriodicalId":393724,"journal":{"name":"2017 IEEE 47th International Symposium on Multiple-Valued Logic (ISMVL)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133064117","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Phase Semantics for Multilattice Formalism 多格形式的相语义
2017 IEEE 47th International Symposium on Multiple-Valued Logic (ISMVL) Pub Date : 2017-05-01 DOI: 10.1109/ISMVL.2017.13
N. Kamide
{"title":"Phase Semantics for Multilattice Formalism","authors":"N. Kamide","doi":"10.1109/ISMVL.2017.13","DOIUrl":"https://doi.org/10.1109/ISMVL.2017.13","url":null,"abstract":"A new logic called linear multilattice logic (LMLn), which is a substructural refinement of Shramko's multilattice logic, is introduced as a Gentzen-type sequent calculus. A phase semantics for LMLn is introduced, and the completeness theorem with respect to this semantics is proved.","PeriodicalId":393724,"journal":{"name":"2017 IEEE 47th International Symposium on Multiple-Valued Logic (ISMVL)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121172114","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Discovery of Multiple-Valued Bent Functions in Galois Field and Reed-Muller-Fourier Domains 伽罗瓦域和Reed-Muller-Fourier域中多值弯曲函数的发现
2017 IEEE 47th International Symposium on Multiple-Valued Logic (ISMVL) Pub Date : 2017-05-01 DOI: 10.1109/ISMVL.2017.17
Milos Radmanovic, R. Stankovic
{"title":"Discovery of Multiple-Valued Bent Functions in Galois Field and Reed-Muller-Fourier Domains","authors":"Milos Radmanovic, R. Stankovic","doi":"10.1109/ISMVL.2017.17","DOIUrl":"https://doi.org/10.1109/ISMVL.2017.17","url":null,"abstract":"Multiple-valued bent functions are a special class of functions which have the highest possible nonlinearity. As the multiple-valued order and number of variables of the functions increases, the probability of discovery of bent functions extremely decreases. Thus, this paper presents a method for random discovery of bent functions in Galois Field and Reed-Muller-Fourier domains. Experimental results are included in order to verify that the proposed computational method reduces the time needed for discovery of random bent ternary and quaternary functions and, in this way, might extend the possibilities for their practical application.","PeriodicalId":393724,"journal":{"name":"2017 IEEE 47th International Symposium on Multiple-Valued Logic (ISMVL)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122033665","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
On the Nonexistence of Minimal Strong Partial Clones 关于极小强部分克隆的不存在性
2017 IEEE 47th International Symposium on Multiple-Valued Logic (ISMVL) Pub Date : 2017-05-01 DOI: 10.1109/ISMVL.2017.43
Miguel Couceiro, L. Haddad, Karsten Schölzel
{"title":"On the Nonexistence of Minimal Strong Partial Clones","authors":"Miguel Couceiro, L. Haddad, Karsten Schölzel","doi":"10.1109/ISMVL.2017.43","DOIUrl":"https://doi.org/10.1109/ISMVL.2017.43","url":null,"abstract":"Let k be a k-element set. We show that the lattice of all strong partial clones on k has no minimal elements. Moreover, we show that if C is a strong partial clone, then the family of all partial subclones of C is of continuum cardinality. We also show that in almost all cases, every strong partial clone contains a family of continuum cardinality of strong partial subclones.","PeriodicalId":393724,"journal":{"name":"2017 IEEE 47th International Symposium on Multiple-Valued Logic (ISMVL)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125351477","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
On the Fault Tolerance of Stochastic Decoders 随机解码器的容错性研究
2017 IEEE 47th International Symposium on Multiple-Valued Logic (ISMVL) Pub Date : 2017-05-01 DOI: 10.1109/ISMVL.2017.50
Assem Hussein, M. Elmasry, V. Gaudet
{"title":"On the Fault Tolerance of Stochastic Decoders","authors":"Assem Hussein, M. Elmasry, V. Gaudet","doi":"10.1109/ISMVL.2017.50","DOIUrl":"https://doi.org/10.1109/ISMVL.2017.50","url":null,"abstract":"This paper investigates the capability of iterative decoders based on stochastic computing (stochastic decoders) to tolerate circuit soft errors while maintaining good bit error rate performance and low error floors in the context of low-density parity-check (LDPC) coding. Soft errors can be intended faults as a result of either VDD scaling to reduce power consumption or overclocking the system to achieve a higher throughput. They can also be unintended faults as a result of temperature or process variations. We developed two models to emulate these circuit errors at the system level. We apply our models to two standardized LDPC codes (10GBASE-T and WiMAX). Simulation results show that stochastic decoding is very tolerant to faults and errors. Hence, stochastic decoding can be very useful in systems with very low power or high performance requirements where we can push the limits of power or speed by lowering VDD or highly overclocking the system while maintaining good performance.","PeriodicalId":393724,"journal":{"name":"2017 IEEE 47th International Symposium on Multiple-Valued Logic (ISMVL)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124280502","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
CMOS-Compatible Ternary Device Platform for Physical Synthesis of Multi-valued Logic Circuits 多值逻辑电路物理合成的cmos兼容三元器件平台
2017 IEEE 47th International Symposium on Multiple-Valued Logic (ISMVL) Pub Date : 2017-05-01 DOI: 10.1109/ISMVL.2017.48
S. Shin, Esan Jang, Jae Won Jeong, K. Kim
{"title":"CMOS-Compatible Ternary Device Platform for Physical Synthesis of Multi-valued Logic Circuits","authors":"S. Shin, Esan Jang, Jae Won Jeong, K. Kim","doi":"10.1109/ISMVL.2017.48","DOIUrl":"https://doi.org/10.1109/ISMVL.2017.48","url":null,"abstract":"We propose the feasible and scalable ternary CMOS (T-CMOS) device platform for a fully CMOS-compatible physical synthesis of multi-valued logic (MVL) circuits. By developing the compact model of T-CMOS and verifying the physical model parameters with experimental data, the T-CMOS design framework based on standard ternary inverter (STI) is presented for static noise margin (SNM) enhancement and performance analysis of ternary logic gates.","PeriodicalId":393724,"journal":{"name":"2017 IEEE 47th International Symposium on Multiple-Valued Logic (ISMVL)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126531483","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
OR-Inverter Graphs for the Synthesis of Optical Circuits 用于光电路合成的or -逆变图
2017 IEEE 47th International Symposium on Multiple-Valued Logic (ISMVL) Pub Date : 2017-05-01 DOI: 10.1109/ISMVL.2017.31
Arighna Deb, R. Wille, R. Drechsler
{"title":"OR-Inverter Graphs for the Synthesis of Optical Circuits","authors":"Arighna Deb, R. Wille, R. Drechsler","doi":"10.1109/ISMVL.2017.31","DOIUrl":"https://doi.org/10.1109/ISMVL.2017.31","url":null,"abstract":"The advances in silicon photonics motivate theconsideration of optical circuits as a promising circuit technology. Recently, synthesis for this kind of circuits received significantattention. However, neither the corresponding function descriptions nor the resulting synthesis approaches explicitly consideredhow optical circuits actually conduct computations – eventuallyleading to circuits of improvable quality. In this work, we presenta synthesis flow which has explicitly been developed for thistechnology. To this end, we introduce and exploit OR-Invertergraphs (OIGs) – a data-structure which is particularly suitedfor the design of optical circuits. Experimental results confirmthe efficacy of the OIG structure and the resulting synthesisapproach. Compared to several alternative solutions – relyingon conventional function representations – the number of gatescan be reduced by half or even significantly more than that.","PeriodicalId":393724,"journal":{"name":"2017 IEEE 47th International Symposium on Multiple-Valued Logic (ISMVL)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134105774","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
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