2017 IEEE 47th International Symposium on Multiple-Valued Logic (ISMVL)最新文献_第4页

Exact Synthesis of Ternary Reversible Functions Using Ternary Toffoli Gates 利用三元Toffoli门精确合成三元可逆函数

2017 IEEE 47th International Symposium on Multiple-Valued Logic (ISMVL) Pub Date : 2017-05-01 DOI: 10.1109/ISMVL.2017.51

Abhoy Kole, P. Rani, K. Datta, I. Sengupta, R. Drechsler

{"title":"Exact Synthesis of Ternary Reversible Functions Using Ternary Toffoli Gates","authors":"Abhoy Kole, P. Rani, K. Datta, I. Sengupta, R. Drechsler","doi":"10.1109/ISMVL.2017.51","DOIUrl":"https://doi.org/10.1109/ISMVL.2017.51","url":null,"abstract":"Realization of logic functions using ternary reversible logic is known to requirelesser number of lines as compared to conventionalbinary reversible logic. This aspect of ternary reversible logic has motivated researchers to explore various synthesis approaches in the past. Existing synthesis methods require additional lines (called ancilla lines)for synthesis, which is expensive from the quantum implementation pointof view. There is no reported work for ternary reversible logic synthesisthat require the minimum possible number of gates and also lines. Thisclass of synthesis methods is called exact synthesis. In this paper two exact synthesis methods for ternary reversible logic have been proposed for the first time, one based on booleansatisfiability (SAT) and the other based on level-constrained heuristic search technique. A permutation representing a reversible ternary truth table is given as input, and a reversible circuit consisting ofgeneralized ternary Toffoli gates that implements the permutationis obtained as output. Experimental studies have been carried out on various randomly generatedternary reversible functions.","PeriodicalId":393724,"journal":{"name":"2017 IEEE 47th International Symposium on Multiple-Valued Logic (ISMVL)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126217345","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 11

On the Interval of Boolean Strong Partial Clones Containing Only Projections as Total Operations 关于只含投影的布尔强部分克隆作为全运算的区间

2017 IEEE 47th International Symposium on Multiple-Valued Logic (ISMVL) Pub Date : 2017-05-01 DOI: 10.1109/ISMVL.2017.27

Miguel Couceiro, L. Haddad, Victor Lagerqvist, Biman Roy

引用次数: 4

Error Bounded Exact BDD Minimization in Approximate Computing 近似计算中的误差有界精确BDD最小化

2017 IEEE 47th International Symposium on Multiple-Valued Logic (ISMVL) Pub Date : 2017-05-01 DOI: 10.1109/ISMVL.2017.11

Saman Fröhlich, Daniel Große, R. Drechsler

引用次数: 7

Fine-Grain Pipelined Reconfigurable VLSI Architecture Based on Multiple-Valued Multiplexer Logic 基于多值复用逻辑的细粒度流水线可重构VLSI结构

2017 IEEE 47th International Symposium on Multiple-Valued Logic (ISMVL) Pub Date : 2017-05-01 DOI: 10.1109/ISMVL.2017.45

Katsuhiko Shimabukuro, M. Kameyama

引用次数: 4

Deep Learning for Autonomous Vehicles 自动驾驶汽车的深度学习

2017 IEEE 47th International Symposium on Multiple-Valued Logic (ISMVL) Pub Date : 2017-05-01 DOI: 10.1109/ISMVL.2017.49

B. Kisačanin

引用次数: 23

Classifying Functions with Exact Synthesis 精确综合函数分类

2017 IEEE 47th International Symposium on Multiple-Valued Logic (ISMVL) Pub Date : 2017-05-01 DOI: 10.1109/ISMVL.2017.44

Winston Haaswijk, Eleonora Testa, Mathias Soeken, G. Micheli

引用次数: 10

Multi-valued Decision Diagrams for k-Out-of-n Three-State Systems k- out -n三态系统的多值决策图

2017 IEEE 47th International Symposium on Multiple-Valued Logic (ISMVL) Pub Date : 2017-05-01 DOI: 10.1109/ISMVL.2017.38

M. Kvassay, E. Zaitseva, V. Levashenko, J. Kostolny

引用次数: 2

A Systematic Design of Tamper-Resistant Galois-Field Arithmetic Circuits Based on Threshold Implementation with (d + 1) Input Shares 基于(d + 1)输入份额门限实现的抗篡改伽罗瓦场算术电路系统设计

2017 IEEE 47th International Symposium on Multiple-Valued Logic (ISMVL) Pub Date : 2017-05-01 DOI: 10.1109/ISMVL.2017.35

Rei Ueno, N. Homma, T. Aoki

引用次数: 10

Three Classes of Closed Sets of Monomials 单项式的三类闭集

2017 IEEE 47th International Symposium on Multiple-Valued Logic (ISMVL) Pub Date : 2017-05-01 DOI: 10.1109/ISMVL.2017.46

Hajime Machida, J. Pantović

引用次数: 3

Analog-to-Digital Converters Using Not Multi-level But Multi-bit Feedback Paths 使用多比特反馈路径而非多级的模数转换器

2017 IEEE 47th International Symposium on Multiple-Valued Logic (ISMVL) Pub Date : 2017-05-01 DOI: 10.1109/ISMVL.2017.30

T. Waho

引用次数: 6