A Systematic Design of Tamper-Resistant Galois-Field Arithmetic Circuits Based on Threshold Implementation with (d + 1) Input Shares

This paper presents a systematic design of tamperresistantGalois-Field (GF) arithmetic circuits based on ThresholdImplementation (TI) where a secret variable is represented withmultiple variables, called shares, given by random numbers. TI isone of the countermeasures against Differential Power Analysis(DPA) on cryptographic hardware. The security order of TIdepends on the number of shares. The minimum number ofshares to be resistant dth-order DPA is said to be (d+1). Whilethe construction of GF arithmetic circuits of quadratic functionbased on TI with (d + 1) shares is known, it is not known howto construct other types of circuits based on it. In this paper, wepresent a generalization and systematic method of constructingthe TI with (d + 1) input shares for any kind of GF arithmeticcircuit in order to design a larger variety of tamper-resistantGF arithmetic circuits. We then apply the proposed method toa cryptographic hardware design in order to demonstrate its efficiency.