发布求助
文献互助 智能选刊 最新文献

2017 IEEE 47th International Symposium on Multiple-Valued Logic (ISMVL)最新文献

筛选
英文 中文
A Random Forest Using a Multi-valued Decision Diagram on an FPGA 基于FPGA的多值决策图随机森林
2017 IEEE 47th International Symposium on Multiple-Valued Logic (ISMVL) Pub Date : 2017-05-22 DOI: 10.1109/ISMVL.2017.40
Hiroki Nakahara, Akira Jinguji, S. Sato, Tsutomu Sasao
{"title":"A Random Forest Using a Multi-valued Decision Diagram on an FPGA","authors":"Hiroki Nakahara, Akira Jinguji, S. Sato, Tsutomu Sasao","doi":"10.1109/ISMVL.2017.40","DOIUrl":"https://doi.org/10.1109/ISMVL.2017.40","url":null,"abstract":"A random forest (RF) is a kind of an ensemblemachine learning algorithm used for a classification and aregression. It consists of multiple decision trees that are built fromrandomly sampled data. The RF has a simple, fast learning, andidentification capability compared with other machine learningalgorithms. It is widely used for various recognition systems. Theconventional RF consisted of binary decision trees (BDTs), whilein this paper, we used a multi-valued decision diagrams (MDDs). In the MDD, each variable appears only once on a path, however, in the BDT, some variable may appear multiple times. Sincethe path length is short in the MDD, it can be evaluated at ahigh speed. The disadvantage is that the number of nodes inthe MDD increases with O(2N), where N denotes the numberof input variables. Fortunately, random forests encourage to usethe small number of N for each tree in order to avoid overfitting. Therefore, in several data sets used in the experimental, the number of nodes did not increase even if the MDD wasused. To reduce the development time, the Altera SDK forOpenCL (AOCL), a kind of a high-level synthesis tool, was used. To accelerate the RF classification using the AOCL, we proposethe fully pipelined architecture to increase the memory bandwidthusing on-chip memories on the FPGA. Also, we apply optimalprecision fixed point representation instead of 32 bit floating pointone. We compared the performance with the CPU and the GPUimplementations. As for the LPS (lookups per second), the FPGArealization was 10.7 times faster than the GPU one, and it was14.0 times faster than the CPU one. As for the LPS per powerconsumption, the FPGA realization was 61.3 times better thanthe GPU one, and it was 12.1 times better than the CPU one.","PeriodicalId":393724,"journal":{"name":"2017 IEEE 47th International Symposium on Multiple-Valued Logic (ISMVL)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2017-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122503141","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 23
Natural Deduction for Connexive Paraconsistent Quantum Logic 连接副协调量子逻辑的自然演绎
2017 IEEE 47th International Symposium on Multiple-Valued Logic (ISMVL) Pub Date : 2017-05-22 DOI: 10.1109/ISMVL.2017.12
N. Kamide
{"title":"Natural Deduction for Connexive Paraconsistent Quantum Logic","authors":"N. Kamide","doi":"10.1109/ISMVL.2017.12","DOIUrl":"https://doi.org/10.1109/ISMVL.2017.12","url":null,"abstract":"In this study, a new logic called the connexive paraconsistent quantum logic is introduced as a common denominator of a paraconsistent logic and a quantum logic. A natural deduction system for this logic is introduced, and the weak normalization theorem for this system is shown. A typed lambda calculus for the implication-negation fragment of this logic is developed on the basis of the Curry-Howard correspondence. The strong normalization theorem for this calculus is proved.","PeriodicalId":393724,"journal":{"name":"2017 IEEE 47th International Symposium on Multiple-Valued Logic (ISMVL)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2017-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123897658","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Evaluation of Stochastic Cascaded IIR Filters 随机级联IIR滤波器的评价
2017 IEEE 47th International Symposium on Multiple-Valued Logic (ISMVL) Pub Date : 2017-05-22 DOI: 10.1109/ISMVL.2017.25
N. Onizawa, S. Koshita, S. Sakamoto, M. Kawamata, T. Hanyu
{"title":"Evaluation of Stochastic Cascaded IIR Filters","authors":"N. Onizawa, S. Koshita, S. Sakamoto, M. Kawamata, T. Hanyu","doi":"10.1109/ISMVL.2017.25","DOIUrl":"https://doi.org/10.1109/ISMVL.2017.25","url":null,"abstract":"Stochastic cascaded IIR filters are used for area-efficient complicated filters in hardware, such as gammatone and gammachirp filters, but the effectiveness of the cascaded form has not been studied in stochastic computation. To evaluate the performance of the stochastic cascaded IIR filters, stochastic direct-form IIR filters are also designed as a baseline filter. The performance of both stochastic filters are simulated in MATLAB and compared with floating-point results in different orders and different stochastic bit lengths. The simulation results show that the cascaded form reduces errors in comparison with the direct form in stochastic IIR filters as well as the well-known effectiveness of the cascaded form in digital IIR filters. In addition, some interesting features of the stochastic IIR filters such as oscillations are exhibited, which are discussed based on spectral analysis.","PeriodicalId":393724,"journal":{"name":"2017 IEEE 47th International Symposium on Multiple-Valued Logic (ISMVL)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2017-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128717802","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Hintikka Style Game Rules for Semi-Fuzzy Quantifiers 半模糊量词的Hintikka风格游戏规则
2017 IEEE 47th International Symposium on Multiple-Valued Logic (ISMVL) Pub Date : 2017-05-22 DOI: 10.1109/ISMVL.2017.57
C. Fermüller, M. Hofer
{"title":"Hintikka Style Game Rules for Semi-Fuzzy Quantifiers","authors":"C. Fermüller, M. Hofer","doi":"10.1109/ISMVL.2017.57","DOIUrl":"https://doi.org/10.1109/ISMVL.2017.57","url":null,"abstract":"Extending Hintikka's game for the evaluation ofclassical formulas, we explore the realm of quantifier rules thatcan be defined by combining several moves consisting of choicesby the two strategic players, but also by a third non-strategicplayer 'Nature', representing random choices. The simple formatof Hintikka-style games is compared to the seemingly much moregeneral one of Giles's game for Lukasiewicz logic.","PeriodicalId":393724,"journal":{"name":"2017 IEEE 47th International Symposium on Multiple-Valued Logic (ISMVL)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2017-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133339137","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Skipping Embedding in the Design of Reversible Circuits 可逆电路设计中的跳过嵌入
2017 IEEE 47th International Symposium on Multiple-Valued Logic (ISMVL) Pub Date : 2017-05-22 DOI: 10.1109/ISMVL.2017.19
Alwin Zulehner, R. Wille
{"title":"Skipping Embedding in the Design of Reversible Circuits","authors":"Alwin Zulehner, R. Wille","doi":"10.1109/ISMVL.2017.19","DOIUrl":"https://doi.org/10.1109/ISMVL.2017.19","url":null,"abstract":"Synthesis of reversible circuits finds application in many promising domains but has to deal with the fact that the underlying circuits require a unique mapping from the inputs to the outputs. Existing solutions addressed this problem by additionally performing a so-called embedding process prior to synthesis or by naively mapping building blocks of conventional logic to their corresponding reversible counterparts. This leads to solutions that either suffer from limited scalability or yield circuits with a huge number of additionally required circuit lines. In this work, we conduct investigations to overcome these problems. To this end, we simply ignore the fact that an arbitrary Boolean function to be synthesized might be non-reversible and deal with the resulting problem of ensuring a unique input/output mapping during the actual synthesis process. Experimental evaluations indicate that, following this approach, could provide the basis for an alternative synthesis scheme that allows for synthesizing arbitrary Boolean functions in reasonable time and without the need of a prior embedding process.","PeriodicalId":393724,"journal":{"name":"2017 IEEE 47th International Symposium on Multiple-Valued Logic (ISMVL)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2017-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123309696","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Algebraic and Combinatorial Methods for Reducing the Number of Variables of Partially Defined Discrete Functions 部分定义离散函数的变量数减少的代数和组合方法
2017 IEEE 47th International Symposium on Multiple-Valued Logic (ISMVL) Pub Date : 2017-05-22 DOI: 10.1109/ISMVL.2017.23
J. Astola, P. Astola, R. Stankovic, I. Tabus
{"title":"Algebraic and Combinatorial Methods for Reducing the Number of Variables of Partially Defined Discrete Functions","authors":"J. Astola, P. Astola, R. Stankovic, I. Tabus","doi":"10.1109/ISMVL.2017.23","DOIUrl":"https://doi.org/10.1109/ISMVL.2017.23","url":null,"abstract":"Applications of pattern recognition, design of faulttolerant systems and communications have key problems that arenaturally described by partially defined (incompletely defined)discrete functions. Such partially defined functions arising frompractical demands usually have a large number of variables andso their direct implementations require complex systems. Thusit is important to have at hand an efficient method to reducethe number of their variables. Here we review recent results tolinearly decompose a discrete function using a transform thatcan be efficiently implemented as a Galois field deconvolution. We also study the question: What are the general bounds for thedimension of the range space for an arbitrary linear transformto reduce a partially defined discrete function? We derive abound for the dimension of the range for arbitrary lineartransformation. We also estimate how good linear decompositioncan be obtained by the use of random transformations and showthat with a randomly generated transform we can reach theabove discussed bound.","PeriodicalId":393724,"journal":{"name":"2017 IEEE 47th International Symposium on Multiple-Valued Logic (ISMVL)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2017-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130236062","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A Novel Ternary Multiplier Based on Ternary CMOS Compact Model 基于三进制CMOS紧凑模型的新型三进制乘法器
2017 IEEE 47th International Symposium on Multiple-Valued Logic (ISMVL) Pub Date : 2017-05-22 DOI: 10.1109/ISMVL.2017.52
Yesung Kang, Jaewoo Kim, Sunmin Kim, S. Shin, Esan Jang, Jae Won Jeong, K. Kim, Seokhyeong Kang
{"title":"A Novel Ternary Multiplier Based on Ternary CMOS Compact Model","authors":"Yesung Kang, Jaewoo Kim, Sunmin Kim, S. Shin, Esan Jang, Jae Won Jeong, K. Kim, Seokhyeong Kang","doi":"10.1109/ISMVL.2017.52","DOIUrl":"https://doi.org/10.1109/ISMVL.2017.52","url":null,"abstract":"Multiple-valued logic (MVL) has potential advantagesfor energy-efficient design by reducing a circuit complexity. Because of physical device and circuit realization issues, however, there are relatively small number of researches on MVL circuitdesigns. We design a novel ternary multiplier based on a ternaryCMOS (T-CMOS) compact model. To estimate performance andenergy efficiency of our ternary design, we construct a standardternary-cell library and exploit a ternary static timing analysis(T-STA). The proposed ternary multiplier design achieves significant total power reduction and performance improvement over conventional ternary design.","PeriodicalId":393724,"journal":{"name":"2017 IEEE 47th International Symposium on Multiple-Valued Logic (ISMVL)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2017-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123638704","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 24
Exploiting Many-Valued Variables in MaxSAT 利用MaxSAT中的多值变量
2017 IEEE 47th International Symposium on Multiple-Valued Logic (ISMVL) Pub Date : 2017-05-22 DOI: 10.1109/ISMVL.2017.42
Josep Argelich, Chu Min Li, F. Manyà
{"title":"Exploiting Many-Valued Variables in MaxSAT","authors":"Josep Argelich, Chu Min Li, F. Manyà","doi":"10.1109/ISMVL.2017.42","DOIUrl":"https://doi.org/10.1109/ISMVL.2017.42","url":null,"abstract":"Solving combinatorial optimization problems by reducing them to MaxSAT has shown to be a competitive problem solving approach. Since a lot of optimization problems have many-valued variables, we propose to exploit the domain information of the many-valued variables to enhance MaxSAT-based problem solving: first, we define a new way of encoding weighted maximum constraint satisfaction problems to both Boolean MaxSAT and many-valued MaxSAT, and second, we define a variable selection heuristic that takes into account the domain information and allow us to easily implement a many-valued MaxSAT solver. Moreover, the empirical results provide evidence of the good performance of the new encodings and the new branching heuristic on a representative set of instances.","PeriodicalId":393724,"journal":{"name":"2017 IEEE 47th International Symposium on Multiple-Valued Logic (ISMVL)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2017-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130152039","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
PAM-4 Eye Diagram Analysis and Its Monitoring Technique for Adaptive Pre-Emphasis for Multi-valued Data Transmissions 多值数据传输自适应预强调PAM-4眼图分析及其监测技术
2017 IEEE 47th International Symposium on Multiple-Valued Logic (ISMVL) Pub Date : 2017-05-22 DOI: 10.1109/ISMVL.2017.29
Y. Yuminaka, Takuya Kitamura, Yosuke Iijima
{"title":"PAM-4 Eye Diagram Analysis and Its Monitoring Technique for Adaptive Pre-Emphasis for Multi-valued Data Transmissions","authors":"Y. Yuminaka, Takuya Kitamura, Yosuke Iijima","doi":"10.1109/ISMVL.2017.29","DOIUrl":"https://doi.org/10.1109/ISMVL.2017.29","url":null,"abstract":"To address the ever-increasing demand for highseed interconnectivity between VLSI systems, the emerging IEEE 802.3bs and CEI-56G standards support a maximum data rate of 400Gb/s. A significant challenge at these data rates is overcoming the bit errors caused by intersymbol interference (ISI) in bandwidth-limited legacy channels. To reduce the bandwidth limitation by half, 4-level pulse amplitude modulation (PAM-4) signaling, which transmits two bits per symbol at a slower symbol rate, is employed. However, compared to that of binary non-return-to-zero (NRZ) signaling, PAM-4 signaling has four distinct levels and significantly more complex data transitions. In this paper, we explore the properties of PAM-4 eye diagrams to realize an adaptive pre-emphasis method for PAM-4 data transmissions. Moreover, we extend conventional eye opening monitoring techniques for NRZ signaling to PAM-4 signaling based on folding the histogram of the probability density function of each level.","PeriodicalId":393724,"journal":{"name":"2017 IEEE 47th International Symposium on Multiple-Valued Logic (ISMVL)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2017-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131741263","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Extensions to the Reversible Hardware Description Language SyReC 可逆硬件描述语言SyReC的扩展
2017 IEEE 47th International Symposium on Multiple-Valued Logic (ISMVL) Pub Date : 2017-05-22 DOI: 10.1109/ISMVL.2017.41
Zaid Al-Wardi, R. Wille, R. Drechsler
{"title":"Extensions to the Reversible Hardware Description Language SyReC","authors":"Zaid Al-Wardi, R. Wille, R. Drechsler","doi":"10.1109/ISMVL.2017.41","DOIUrl":"https://doi.org/10.1109/ISMVL.2017.41","url":null,"abstract":"Hardware Description Languages (HDL) are proposed to facilitate the design of complex circuits and to allow for scalable synthesis. While rather established for conventional circuits, HDLs for the design and synthesis of reversible circuits are at the beginning. SyReC is a representative of such an HDL which already has successfully be applied to realize complexfunctionality in reversible logic. Nevertheless, the grammar and, by this, the functional scope of this language is rather limited. In this work, we propose extensions to the SyReC HDL which will enhance the usability of the language. For each extension, we additionally provide corresponding synthesis schemes. Overall, this yields a new (extended) SyReC HDL, which will simplify the design and realization of corresponding circuits.","PeriodicalId":393724,"journal":{"name":"2017 IEEE 47th International Symposium on Multiple-Valued Logic (ISMVL)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2017-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122210303","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
下一页 尾页
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整，为了账户安全，请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
请完成安全验证×
相关产品
×
本文献相关产品
联系我们：info@booksci.cn Book学术提供免费学术资源搜索服务，方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号：481959085
Book学术官方微信