{"title":"CMOS-Compatible Ternary Device Platform for Physical Synthesis of Multi-valued Logic Circuits","authors":"S. Shin, Esan Jang, Jae Won Jeong, K. Kim","doi":"10.1109/ISMVL.2017.48","DOIUrl":null,"url":null,"abstract":"We propose the feasible and scalable ternary CMOS (T-CMOS) device platform for a fully CMOS-compatible physical synthesis of multi-valued logic (MVL) circuits. By developing the compact model of T-CMOS and verifying the physical model parameters with experimental data, the T-CMOS design framework based on standard ternary inverter (STI) is presented for static noise margin (SNM) enhancement and performance analysis of ternary logic gates.","PeriodicalId":393724,"journal":{"name":"2017 IEEE 47th International Symposium on Multiple-Valued Logic (ISMVL)","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"7","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2017 IEEE 47th International Symposium on Multiple-Valued Logic (ISMVL)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISMVL.2017.48","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 7
Abstract
We propose the feasible and scalable ternary CMOS (T-CMOS) device platform for a fully CMOS-compatible physical synthesis of multi-valued logic (MVL) circuits. By developing the compact model of T-CMOS and verifying the physical model parameters with experimental data, the T-CMOS design framework based on standard ternary inverter (STI) is presented for static noise margin (SNM) enhancement and performance analysis of ternary logic gates.