On the Fault Tolerance of Stochastic Decoders

This paper investigates the capability of iterative decoders based on stochastic computing (stochastic decoders) to tolerate circuit soft errors while maintaining good bit error rate performance and low error floors in the context of low-density parity-check (LDPC) coding. Soft errors can be intended faults as a result of either VDD scaling to reduce power consumption or overclocking the system to achieve a higher throughput. They can also be unintended faults as a result of temperature or process variations. We developed two models to emulate these circuit errors at the system level. We apply our models to two standardized LDPC codes (10GBASE-T and WiMAX). Simulation results show that stochastic decoding is very tolerant to faults and errors. Hence, stochastic decoding can be very useful in systems with very low power or high performance requirements where we can push the limits of power or speed by lowering VDD or highly overclocking the system while maintaining good performance.