IPSJ Transactions on System LSI Design Methodology最新文献_第8页

All-Digital RF Phase-Locked Loops Exploiting Phase Prediction 利用相位预测的全数字射频锁相环

IPSJ Transactions on System LSI Design Methodology Pub Date : 2014-02-02 DOI: 10.2197/IPSJTSLDM.7.2

J. Zhuang, R. Staszewski

引用次数: 0

Dynamic Power Consumption Optimization for Inductive-Coupling based Wireless 3D NoCs 基于电感耦合的无线3D noc动态功耗优化

IPSJ Transactions on System LSI Design Methodology Pub Date : 2014-02-01 DOI: 10.2197/ipsjtsldm.7.27

Hao Zhang, Hiroki Matsutani, M. Koibuchi, H. Amano

引用次数: 2

Energy-efficient High-level Synthesis for HDR Architecture with Multi-stage Clock Gating 基于多级时钟门控的HDR架构高能效综合

IPSJ Transactions on System LSI Design Methodology Pub Date : 2014-01-01 DOI: 10.2197/ipsjtsldm.7.74

Hiroyuki Akasaka, Shin-ya Abe, M. Yanagisawa, N. Togawa

引用次数: 0

A Sophisticated Routing Algorithm in 3D NoC with Fixed TSVs for Low Energy and Latency 一种基于固定tsv的低能量低时延3D NoC路由算法

IPSJ Transactions on System LSI Design Methodology Pub Date : 2014-01-01 DOI: 10.2197/ipsjtsldm.7.101

Xin Jiang, Lian Zeng, Takahiro Watanabe

引用次数: 8

A Delay-variation-aware High-level Synthesis Algorithm for RDR Architectures 面向RDR体系结构的延迟变化感知高级综合算法

IPSJ Transactions on System LSI Design Methodology Pub Date : 2014-01-01 DOI: 10.2197/ipsjtsldm.7.81

Yuta Hagio, M. Yanagisawa, N. Togawa

{"title":"A Delay-variation-aware High-level Synthesis Algorithm for RDR Architectures","authors":"Yuta Hagio, M. Yanagisawa, N. Togawa","doi":"10.2197/ipsjtsldm.7.81","DOIUrl":"https://doi.org/10.2197/ipsjtsldm.7.81","url":null,"abstract":"As device feature size drops, interconnection delays often exceed gate delays. We have to incorporate interconnection delays even in high-level synthesis. Using RDR architectures is one of the effective solutions to this problem. At the same time, process and delay variation also becomes a serious problem which may result in several timing errors. How to deal with this problem is another key issue in high-level synthesis. In this paper, we propose a delay-variation-aware high-level synthesis algorithm for RDR architectures. We first obtain a non-delayed scheduling/binding result and, based on it, we also obtain a delayed scheduling/binding result. By adding several extra functional units to vacant RDR islands, we can have a delayed scheduling/binding result so that its latency is not much increased compared with the non-delayed one. After that, we similarize the two scheduling/binding results by repeatedly modifying their results. We can finally realize non-delayed and delayed scheduling/binding results simultaneously on RDR architecture with almost no area/performance overheads and we can select either one of them depending on post-silicon delay variation. Experimental results show that our algorithm successfully reduces delayed scheduling/binding latency by up to 42.9% compared with the conventional approach.","PeriodicalId":38964,"journal":{"name":"IPSJ Transactions on System LSI Design Methodology","volume":"28 1","pages":"81-90"},"PeriodicalIF":0.0,"publicationDate":"2014-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90826335","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

Reinforcing Random Testing of Arithmetic Optimization of C Compilers by Scaling up Size and Number of Expressions 通过增大表达式的大小和数目来加强C编译器算法优化的随机测试

IPSJ Transactions on System LSI Design Methodology Pub Date : 2014-01-01 DOI: 10.2197/IPSJTSLDM.7.91

Eriko Nagai, Atsushi Hashimoto, N. Ishiura

引用次数: 40

Impact of Resource Sharing and Register Retiming on Area and Performance of FPGA-based Designs 资源共享和寄存器重定时对fpga设计面积和性能的影响

IPSJ Transactions on System LSI Design Methodology Pub Date : 2014-01-01 DOI: 10.2197/ipsjtsldm.7.37

Yuko Hara-Azumi, Toshinobu Matsuba, H. Tomiyama, S. Honda, H. Takada

引用次数: 4

Test and Design-for-Testability Solutions for 3D Integrated Circuits 3D集成电路的测试和可测试性设计解决方案

IPSJ Transactions on System LSI Design Methodology Pub Date : 2014-01-01 DOI: 10.2197/ipsjtsldm.7.56

K. Chakrabarty, Mukesh Agrawal, Sergej Deutsch, Brandon Noia, Ran Wang, Fangming Ye

引用次数: 19

Design Automation for Digital Microfluidic Biochips 数字微流控生物芯片的设计自动化

IPSJ Transactions on System LSI Design Methodology Pub Date : 2014-01-01 DOI: 10.2197/ipsjtsldm.7.16

Tsung-Yi Ho

{"title":"Design Automation for Digital Microfluidic Biochips","authors":"Tsung-Yi Ho","doi":"10.2197/ipsjtsldm.7.16","DOIUrl":"https://doi.org/10.2197/ipsjtsldm.7.16","url":null,"abstract":"Microfluidic biochips are replacing the conventional biochemical analyzers, and are able to integrate onchip all the basic functions for biochemical analysis. The “digital” microfluidic biochips (DMFBs) are manipulating liquids not as a continuous flow, but as discrete droplets on a two-dimensional array of electrodes. Basic microfluidic operations, such as mixing and dilution, are performed on the array, by routing the corresponding droplets on a series of electrodes. The challenges facing biochips are similar to those faced by microelectronics some decades ago. To meet the challenges of increasing design complexity, computer-aided-design (CAD) tools are being developed for DMFBs. This paper provides an overview of DMFBs and describes emerging CAD tools for the automated synthesis and optimization of DMFB designs, from fluidic-level synthesis and chip-level design to testing. Design automations are expected to alleviate the burden of manual optimization of bioassays, time-consuming chip designs, and costly testing and maintenance procedures. With the assistance of CAD tools, users can concentrate on the development and abstraction of nanoscale bioassays while leaving chip optimization and implementation details to CAD tools.","PeriodicalId":38964,"journal":{"name":"IPSJ Transactions on System LSI Design Methodology","volume":"123 1","pages":"16-26"},"PeriodicalIF":0.0,"publicationDate":"2014-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85120954","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 7

Forwarding Unit Generation for Loop Pipelining in High-level Synthesis 高级综合中循环流水线转发单元的生成

IPSJ Transactions on System LSI Design Methodology Pub Date : 2014-01-01 DOI: 10.2197/ipsjtsldm.7.119

Shingo Kusakabe, Kenshu Seto

{"title":"Forwarding Unit Generation for Loop Pipelining in High-level Synthesis","authors":"Shingo Kusakabe, Kenshu Seto","doi":"10.2197/ipsjtsldm.7.119","DOIUrl":"https://doi.org/10.2197/ipsjtsldm.7.119","url":null,"abstract":"In the loop pipelining of high-level synthesis, the reduction of initiation intervals (IIs) is very important. Existing loop pipelining techniques, however, pessimistically assumes that dependences whose occurrences can be determined only at runtime always occur, resulting in increased IIs. To address this issue, recent work achieves reduced II by a source code transformation which introduces runtime dependence analysis and performs pipeline stalls when the dependences actually occur. Unfortunately, the recent work suffers from the increased execution cycles by frequent pipeline stalls under the frequent occurrences of the dependences. In this paper, we propose a technique to reduce IIs in which data written to memories are also written to registers for such dependences of read-after-write (RAW) type. In our technique, registers which are faster than memories are accessed when the RAW dependences occur. Since the proposed technique achieved the reduction of the execution cycles by 34% with 15% gate count increase on average for three examples compared to the state-of-the-art technique, the proposed technique is effective for synthesizing high-speed circuits with loop pipelining.","PeriodicalId":38964,"journal":{"name":"IPSJ Transactions on System LSI Design Methodology","volume":"29 1","pages":"119-124"},"PeriodicalIF":0.0,"publicationDate":"2014-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80304021","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0