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IPSJ Transactions on System LSI Design Methodology最新文献

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Parallelizing Random and SAT-based Verification Processes for Improving Toggle Coverage 并行化随机和基于sat的验证过程以提高切换覆盖率
IPSJ Transactions on System LSI Design Methodology Pub Date : 2023-01-01 DOI: 10.2197/ipsjtsldm.16.45
K. Hamaguchi
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引用次数: 0
Feature Vectors Based on Wire Width and Distance for Lithography Hotspot Detection 基于线宽和距离的光刻热点检测特征向量
IPSJ Transactions on System LSI Design Methodology Pub Date : 2023-01-01 DOI: 10.2197/ipsjtsldm.16.2
Gaku Kataoka, M. Yamamoto, Masato Inagi, Shinobu Nagayama, S. Wakabayashi
{"title":"Feature Vectors Based on Wire Width and Distance for Lithography Hotspot Detection","authors":"Gaku Kataoka, M. Yamamoto, Masato Inagi, Shinobu Nagayama, S. Wakabayashi","doi":"10.2197/ipsjtsldm.16.2","DOIUrl":"https://doi.org/10.2197/ipsjtsldm.16.2","url":null,"abstract":"","PeriodicalId":38964,"journal":{"name":"IPSJ Transactions on System LSI Design Methodology","volume":"31 1","pages":"2-11"},"PeriodicalIF":0.0,"publicationDate":"2023-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87215897","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Measurement Results of Real Circuit Delay Degradation under Realistic Workload 实际工作负载下真实电路时延退化的测量结果
IPSJ Transactions on System LSI Design Methodology Pub Date : 2023-01-01 DOI: 10.2197/ipsjtsldm.16.27
K. Shimamura, Takeshi Takehara, Naohiro Ikeda
{"title":"Measurement Results of Real Circuit Delay Degradation under Realistic Workload","authors":"K. Shimamura, Takeshi Takehara, Naohiro Ikeda","doi":"10.2197/ipsjtsldm.16.27","DOIUrl":"https://doi.org/10.2197/ipsjtsldm.16.27","url":null,"abstract":"","PeriodicalId":38964,"journal":{"name":"IPSJ Transactions on System LSI Design Methodology","volume":"22 1","pages":"27-34"},"PeriodicalIF":0.0,"publicationDate":"2023-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79426745","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A CMOS-compatible Non-volatile Memory Element using Fishbone-in-cage Capacitor 一种采用鱼骨笼式电容的cmos兼容非易失性存储器元件
IPSJ Transactions on System LSI Design Methodology Pub Date : 2023-01-01 DOI: 10.2197/ipsjtsldm.16.35
Ippei Tanaka, N. Miyagawa, Tomoya Kimura, Takashi Imagawa, H. Ochi
{"title":"A CMOS-compatible Non-volatile Memory Element using Fishbone-in-cage Capacitor","authors":"Ippei Tanaka, N. Miyagawa, Tomoya Kimura, Takashi Imagawa, H. Ochi","doi":"10.2197/ipsjtsldm.16.35","DOIUrl":"https://doi.org/10.2197/ipsjtsldm.16.35","url":null,"abstract":"","PeriodicalId":38964,"journal":{"name":"IPSJ Transactions on System LSI Design Methodology","volume":"48 1","pages":"35-44"},"PeriodicalIF":0.0,"publicationDate":"2023-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81401337","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
LLVM-C2RTL: C/C++ Based System Level RTL Design Framework Using LLVM Compiler Infrastructure LLVM- c2rtl:基于C/ c++的系统级RTL设计框架
IPSJ Transactions on System LSI Design Methodology Pub Date : 2023-01-01 DOI: 10.2197/ipsjtsldm.16.12
Tamon Sadasue, T. Isshiki
{"title":"LLVM-C2RTL: C/C++ Based System Level RTL Design Framework Using LLVM Compiler Infrastructure","authors":"Tamon Sadasue, T. Isshiki","doi":"10.2197/ipsjtsldm.16.12","DOIUrl":"https://doi.org/10.2197/ipsjtsldm.16.12","url":null,"abstract":"","PeriodicalId":38964,"journal":{"name":"IPSJ Transactions on System LSI Design Methodology","volume":"93 1","pages":"12-26"},"PeriodicalIF":0.0,"publicationDate":"2023-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85693667","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Parallel Scheduling Attention Mechanism: Generalization and Optimization 并行调度注意机制:概化与优化
IPSJ Transactions on System LSI Design Methodology Pub Date : 2022-01-01 DOI: 10.2197/ipsjtsldm.15.2
Mingfei Yu, Yukio Miyasaka, M. Fujita
{"title":"Parallel Scheduling Attention Mechanism: Generalization and Optimization","authors":"Mingfei Yu, Yukio Miyasaka, M. Fujita","doi":"10.2197/ipsjtsldm.15.2","DOIUrl":"https://doi.org/10.2197/ipsjtsldm.15.2","url":null,"abstract":"","PeriodicalId":38964,"journal":{"name":"IPSJ Transactions on System LSI Design Methodology","volume":"36 1","pages":"2-15"},"PeriodicalIF":0.0,"publicationDate":"2022-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75392197","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Posit Based Multiply-accumulate Unit with Small Quire Size for Deep Neural Networks 一种基于位置的小队列乘累积单元深度神经网络
IPSJ Transactions on System LSI Design Methodology Pub Date : 2022-01-01 DOI: 10.2197/ipsjtsldm.15.16
Yasuhiro Nakahara, Yuta Masuda, M. Kiyama, M. Amagasaki, M. Iida
{"title":"A Posit Based Multiply-accumulate Unit with Small Quire Size for Deep Neural Networks","authors":"Yasuhiro Nakahara, Yuta Masuda, M. Kiyama, M. Amagasaki, M. Iida","doi":"10.2197/ipsjtsldm.15.16","DOIUrl":"https://doi.org/10.2197/ipsjtsldm.15.16","url":null,"abstract":"","PeriodicalId":38964,"journal":{"name":"IPSJ Transactions on System LSI Design Methodology","volume":"2 1","pages":"16-19"},"PeriodicalIF":0.0,"publicationDate":"2022-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79625075","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Scalable Hardware Architecture for fast Gradient Boosted Tree Training 用于快速梯度增强树训练的可扩展硬件架构
IPSJ Transactions on System LSI Design Methodology Pub Date : 2021-01-01 DOI: 10.2197/ipsjtsldm.14.11
Tamon Sadasue, Takuya Tanaka, Ryosuke Kasahara, Arief Darmawan, T. Isshiki
{"title":"Scalable Hardware Architecture for fast Gradient Boosted Tree Training","authors":"Tamon Sadasue, Takuya Tanaka, Ryosuke Kasahara, Arief Darmawan, T. Isshiki","doi":"10.2197/ipsjtsldm.14.11","DOIUrl":"https://doi.org/10.2197/ipsjtsldm.14.11","url":null,"abstract":": Gradient Boosted Tree is a powerful machine learning method that supports both classification and regres- sion, and is widely used in fields requiring high-precision prediction, particularly for various types of tabular data sets. Owing to the recent increase in data size, the number of attributes, and the demand for frequent model updates, a fast and e ffi cient training is required. FPGA is suitable for acceleration with power e ffi ciency because it can realize a domain specific hardware architecture; however it is necessary to flexibly support many hyper-parameters to adapt to various dataset sizes, dataset properties, and system limitations such as memory capacity and logic capacity. We introduce a fully pipelined hardware implementation of Gradient Boosted Tree training and a design framework that enables a versatile hardware system description with high performance and flexibility to realize highly parameterized machine learning models. Experimental results show that our FPGA implementation achieves a 11- to 33-times faster performance and more than 300-times higher power e ffi ciency than a state-of-the-art GPU accelerated software implementation.","PeriodicalId":38964,"journal":{"name":"IPSJ Transactions on System LSI Design Methodology","volume":"23 1","pages":"11-20"},"PeriodicalIF":0.0,"publicationDate":"2021-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91185868","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Computational Lithography Using Machine Learning Models 使用机器学习模型的计算光刻
IPSJ Transactions on System LSI Design Methodology Pub Date : 2021-01-01 DOI: 10.2197/ipsjtsldm.14.2
Y. Shin
{"title":"Computational Lithography Using Machine Learning Models","authors":"Y. Shin","doi":"10.2197/ipsjtsldm.14.2","DOIUrl":"https://doi.org/10.2197/ipsjtsldm.14.2","url":null,"abstract":"Machine learning models have been applied to a wide range of computational lithography applications since around 2010. They provide higher modeling capability, so their application allows modeling of higher accuracy. Many applications which are computationally expensive can take advantage of machine learning models, since a well trained model provides a quick estimation of outcome. This tutorial reviews a number of such computational lithography applications that have been using machine learning models. They include mask optimization with OPC (optical proximity correction) and EPC (etch proximity correction), assist features insertion and their printability check, lithography modeling with optical model and resist model, test patterns, and hotspot detection and correction.","PeriodicalId":38964,"journal":{"name":"IPSJ Transactions on System LSI Design Methodology","volume":"76 1","pages":"2-10"},"PeriodicalIF":0.0,"publicationDate":"2021-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76124171","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Energy-aware Routing of Delivery Drones under Windy Conditions 多风条件下送货无人机的能量感知路径
IPSJ Transactions on System LSI Design Methodology Pub Date : 2021-01-01 DOI: 10.2197/ipsjtsldm.14.30
Satoshi Ito, Hiroki Nishikawa, Xiangbo Kong, Yusuke Funabashi, Atsuya Shibata, Shunsuke Negoro, Ittetsu Taniguchi, Hiroyuki Tomiyama
{"title":"Energy-aware Routing of Delivery Drones under Windy Conditions","authors":"Satoshi Ito, Hiroki Nishikawa, Xiangbo Kong, Yusuke Funabashi, Atsuya Shibata, Shunsuke Negoro, Ittetsu Taniguchi, Hiroyuki Tomiyama","doi":"10.2197/ipsjtsldm.14.30","DOIUrl":"https://doi.org/10.2197/ipsjtsldm.14.30","url":null,"abstract":"","PeriodicalId":38964,"journal":{"name":"IPSJ Transactions on System LSI Design Methodology","volume":"112 1","pages":"30-39"},"PeriodicalIF":0.0,"publicationDate":"2021-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85853949","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
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