IPSJ Transactions on System LSI Design Methodology最新文献_第10页

Energy-efficient High-level Synthesis for HDR Architectures with Clock Gating Based on Concurrency-oriented Scheduling 基于并发调度的时钟门控HDR架构高能效综合

IPSJ Transactions on System LSI Design Methodology Pub Date : 2013-01-01 DOI: 10.2197/ipsjtsldm.6.101

Hiroyuki Akasaka, Shin-ya Abe, M. Yanagisawa, N. Togawa

{"title":"Energy-efficient High-level Synthesis for HDR Architectures with Clock Gating Based on Concurrency-oriented Scheduling","authors":"Hiroyuki Akasaka, Shin-ya Abe, M. Yanagisawa, N. Togawa","doi":"10.2197/ipsjtsldm.6.101","DOIUrl":"https://doi.org/10.2197/ipsjtsldm.6.101","url":null,"abstract":"With the miniaturization of LSIs and its increasing performance, demand for high-functional portable devices has grown significantly. At the same time, battery lifetime and device overheating are leading to major design problems hampering further LSI integration. On the other hand, the ratio of an interconnection delay to a gate delay has continued to increase as device feature size decreases. We have to estimate interconnection delays and reduce energy consumption even in a high-level synthesis stage. In this paper, we propose a high-level synthesis algorithm for huddle-based distributed-register architectures (HDR architectures) with clock gatings based on concurrency-oriented scheduling/functional unit binding. We assume coarse-grained clock gatings to huddles and we focus on the number of control steps, or gating steps, at which we can apply the clock gating to registers in every huddle. We propose two methods to increase gating steps: One is that we try to schedule and bind operations to be performed at the same timing. By adjusting the clock gating timings in a high-level synthesis stage, we expect that we can enhance the effect of clock gatings more than applying clock gatings after logic synthesis. The other is that we try to synthesize huddles such that each of the synthesized huddles includes registers which have similar or the same clock gating timings. At this time, we determine the clock gating timings to minimize all energy consumption including clock tree energy. The experimental results show that our proposed algorithm reduces energy consumption by a maximum of 23.8% compared with several conventional algorithms.","PeriodicalId":38964,"journal":{"name":"IPSJ Transactions on System LSI Design Methodology","volume":"47 1","pages":"101-111"},"PeriodicalIF":0.0,"publicationDate":"2013-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91147408","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

A Method to Reduce Energy Consumption of Conditional Operations with Execution Probabilities 一种降低具有执行概率的条件运算能耗的方法

IPSJ Transactions on System LSI Design Methodology Pub Date : 2013-01-01 DOI: 10.2197/ipsjtsldm.6.60

Kazuhito Ito, Kazuhiko Kameda

引用次数: 0

Loop Fusion with Outer Loop Shifting for High-level Synthesis 高阶合成中外环移位的环融合

IPSJ Transactions on System LSI Design Methodology Pub Date : 2013-01-01 DOI: 10.2197/ipsjtsldm.6.71

Y. Kato, Kenshu Seto

引用次数: 4

An FPGA Implementation of a HOG-based Object Detection Processor 基于hog的目标检测处理器的FPGA实现

IPSJ Transactions on System LSI Design Methodology Pub Date : 2013-01-01 DOI: 10.2197/ipsjtsldm.6.42

Kosuke Mizuno, Yosuke Terachi, Kenta Takagi, S. Izumi, H. Kawaguchi, M. Yoshimoto

引用次数: 14

A non-volatile reconfigurable offloader for wireless sensor nodes 一种用于无线传感器节点的非易失性可重构卸载器

IPSJ Transactions on System LSI Design Methodology Pub Date : 2012-12-25 DOI: 10.1145/2460216.2460232

S. Nakaya, M. Miyamura, N. Sakimura, Yuichi Nakamura, T. Sugibayashi

引用次数: 4

Optimized Communication and Synchronization for Embedded Multiprocessors Using ASIP Methodology 利用ASIP方法优化嵌入式多处理器的通信与同步

IPSJ Transactions on System LSI Design Methodology Pub Date : 2012-10-01 DOI: 10.2197/ipsjtsldm.5.118

Hao Xiao, T. Isshiki, Dongju Li, H. Kunieda, Yuko Nakase, Sadahiro Kimura

{"title":"Optimized Communication and Synchronization for Embedded Multiprocessors Using ASIP Methodology","authors":"Hao Xiao, T. Isshiki, Dongju Li, H. Kunieda, Yuko Nakase, Sadahiro Kimura","doi":"10.2197/ipsjtsldm.5.118","DOIUrl":"https://doi.org/10.2197/ipsjtsldm.5.118","url":null,"abstract":"Inter-processor communication and synchronization are critical problems in embedded multiprocessors. In order to achieve high-speed communication and low-latency synchronization, most recent designs employ dedicated hardware engines to support these communication protocols individually, which is complex, inflexible, and error prone. Thus, this paper motivates the optimization of inter-processor communication and synchronization by using application-specific instruction-set processor (ASIP) techniques. The proposed communication mechanism is based on a set of custom instructions coupled with a low-latency on-chip network, which provides efficient support for both data transfer and process synchronization. By using state-of-the-art ASIP design methodology, we embed the communication functionalities into a base processor, making the proposed mechanism feature ultra low overhead. More importantly, industry-standard compatible programming interfaces supporting both message-passing and shared-memory paradigms are exposed to end-users to ease the software porting. Experimental results show that the bandwidth of the proposed message-passing protocol can achieve up to 703 Mbyte/s @ 200 MHz, and the latency of the proposed synchronization protocol can be reduced by more than 81% when compared with the conventional approach. Moreover, as a case study, we also show the effectiveness of the proposed communication mechanism in a real-life embedded application, WiMedia UWB MAC.","PeriodicalId":38964,"journal":{"name":"IPSJ Transactions on System LSI Design Methodology","volume":"47 1","pages":"118-132"},"PeriodicalIF":0.0,"publicationDate":"2012-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78389873","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 16

An Exact Estimation Algorithm of Error Propagation Probability for Sequential Circuits 时序电路误差传播概率的精确估计算法

IPSJ Transactions on System LSI Design Methodology Pub Date : 2012-08-17 DOI: 10.2197/ipsjtsldm.5.63

Masayoshi Yoshimura, Y. Akamine, Y. Matsunaga

{"title":"An Exact Estimation Algorithm of Error Propagation Probability for Sequential Circuits","authors":"Masayoshi Yoshimura, Y. Akamine, Y. Matsunaga","doi":"10.2197/ipsjtsldm.5.63","DOIUrl":"https://doi.org/10.2197/ipsjtsldm.5.63","url":null,"abstract":"In advanced integrated circuit technology, the soft error tolerance is low. Soft errors ultimately lead to failure in VLSIs. We propose a method for the exact estimation of error propagation probabilities in sequential circuits whose FFs latch failure values. The failure due to soft errors in sequential circuits is defined using the modified product machine. The modified product machine monitors whether failure values appear at any primary output. The behavior of the modified product machine is analyzed with the Markov model. The probabilities that the failure values latched into the flip-flops (FFs) appear at any primary output are calculated from the state transition probabilities of the modified product machine. The time required for solving simultaneous linear equations accounts for a large portion of the execution time. We also propose two acceleration techniques to enable the application of our estimation method to larger scale circuits. These acceleration techniques reduce the number of variables in simultaneous linear equations. We apply the proposed method to ISCAS'89 and MCNC benchmark circuits and estimate error propagation probabilities for sequential circuits. Experimental results show that total execution times for the proposed method with two acceleration techniques are up to 10 times lesser than the total execution times for a naive implementation.","PeriodicalId":38964,"journal":{"name":"IPSJ Transactions on System LSI Design Methodology","volume":"1 1","pages":"63-70"},"PeriodicalIF":0.0,"publicationDate":"2012-08-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77311471","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Energy-efficient High-level Synthesis for HDR Architectures HDR架构的高能效高级综合

IPSJ Transactions on System LSI Design Methodology Pub Date : 2012-08-17 DOI: 10.2197/ipsjtsldm.5.106

Shin-ya Abe, M. Yanagisawa, N. Togawa

引用次数: 13

A Stackable LTE Chip for Cost-effective 3D Systems 用于高性价比3D系统的可堆叠LTE芯片

IPSJ Transactions on System LSI Design Methodology Pub Date : 2012-01-01 DOI: 10.2197/ipsjtsldm.5.2

W. Lafi, D. Lattard, A. Jerraya

引用次数: 4

System-On-Chip for Biologically Inspired Vision Applications 生物启发视觉应用的片上系统

IPSJ Transactions on System LSI Design Methodology Pub Date : 2012-01-01 DOI: 10.2197/ipsjtsldm.5.71

Sungho Park, Ahmed Al-Maashri, K. Irick, A. Chandrashekhar, M. Cotter, Nandhini Chandramoorthy, M. DeBole, N. Vijaykrishnan

引用次数: 22