用于高性价比3D系统的可堆叠LTE芯片

Q4 Engineering
W. Lafi, D. Lattard, A. Jerraya
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引用次数: 4

摘要

为了解决先进制造技术成本过高的问题,一种解决方案是重复使用掩模来解决各种ic。这可以通过一个模块化电路来实现,该电路可以堆叠以构建基于tsv的3D系统,其处理性能适用于多种应用。本文主要研究4G无线通信的应用。我们提出了一种满足SISO(单输入单输出)传输模式的基本电路。通过堆叠同一电路的多个实例,可以解决多个MIMO(多输入多输出)模式。所提出的电路由若干处理单元组成,这些处理单元由3D NoC互连,并由主处理器控制。与2D参考平台相比,所提出的电路在4G电信应用中至少保持相同的性能和功耗,同时降低了总成本。更一般地说,我们的成本分析表明,3D集成效率取决于电路的尺寸和堆叠选项(模对模、模对晶圆和基于中间体的堆叠)。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
A Stackable LTE Chip for Cost-effective 3D Systems
To address the problem of prohibitive cost of advanced fabrication technologies, one solution consists in reusing masks to address a wide range of ICs. This could be achieved by a modular circuit that can be stacked to build TSV-based 3D systems with processing performance adapted to several applications. This paper focuses on 4G wireless telecom applications. We propose a basic circuit that meets the SISO (Single Input Single Output) transmission mode. By stacking multiple instances of this same circuit, it will be possible to address several MIMO (Multiple Input Multiple Output) modes. The proposed circuit is composed of several processing units interconnected by a 3D NoC and controlled by a host processor. Compared to a 2D reference platform, the proposed circuit keeps at least the same performance and power consumption in the context of 4G telecom applications, while reducing total cost. More generally, our cost analysis shows that 3D integration efficiency depends on the size of the circuit and the stacking option (die-to-die, die-to-wafer and interposer-based stacking).
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来源期刊
IPSJ Transactions on System LSI Design Methodology
IPSJ Transactions on System LSI Design Methodology Engineering-Electrical and Electronic Engineering
CiteScore
1.20
自引率
0.00%
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