2017 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED)最新文献

A low power duobinary voltage mode transmitter 一种低功率双电压模式发射机

2017 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED) Pub Date : 2017-08-11 DOI: 10.1109/ISLPED.2017.8009205

Ming-Hung Chien, Yen-Long Lee, J. Goh, Soon-Jyh Chang

引用次数: 2

Tutorial: Tiny light-harvesting photovoltaic charger-supplies 教程:微型光收集光伏充电器

2017 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED) Pub Date : 2017-07-24 DOI: 10.1109/ISLPED.2017.8009152

G. Rincón-Mora

{"title":"Tutorial: Tiny light-harvesting photovoltaic charger-supplies","authors":"G. Rincón-Mora","doi":"10.1109/ISLPED.2017.8009152","DOIUrl":"https://doi.org/10.1109/ISLPED.2017.8009152","url":null,"abstract":"A fundamental challenge wireless microsystems face is size, and in consequence, lifetime because tiny batteries exhaust quickly. Although small fuel cells and atomic sources store more energy than lithium-ion batteries and super capacitors, they source less power, so they cannot power as many functions. Small batteries and capacitors, however, cannot sustain life for long. Thankfully, the environment holds vast amounts of energy. And of typical sources like light, motion, temperature, and radiation, sunlight produces the highest power density, but only when available. Combining photovoltaic (PV) cells with tiny batteries or capacitors can therefore be more compact, reliable, and longer lasting than any one of these technologies alone. Managing a hybrid system of this sort to supply a milliwatt application, however, requires an intelligent, low-loss charger-supply system. This talk surveys and describes how smart PV-sourced microsystems can draw power from tiny PV cells and supplementary power from small batteries to supply a load and replenish the battery with excess PV power. To that end, the material reviews and discusses miniaturized PV cells, power-efficient charger-supply circuits, and reliable feedback controllers. The presentation ends with measurement results from a prototyped example.","PeriodicalId":385714,"journal":{"name":"2017 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2017-07-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120901338","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Charge recycled low power SRAM with integrated write and read assist, for wearable electronics, designed in 7nm FinFET 充电回收低功耗SRAM集成写入和读取辅助，用于可穿戴电子产品，在7nm FinFET设计

2017 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED) Pub Date : 2017-07-24 DOI: 10.1109/ISLPED.2017.8009154

V. Nautiyal, G. Singla, Satinderjit Singh, F. Bohra, J. Dasani, Lalita Gupta, S. Dwivedi

{"title":"Charge recycled low power SRAM with integrated write and read assist, for wearable electronics, designed in 7nm FinFET","authors":"V. Nautiyal, G. Singla, Satinderjit Singh, F. Bohra, J. Dasani, Lalita Gupta, S. Dwivedi","doi":"10.1109/ISLPED.2017.8009154","DOIUrl":"https://doi.org/10.1109/ISLPED.2017.8009154","url":null,"abstract":"A recent trend in the electronics industry is the concept of intelligent wearables and the Internet of Things (IoT) such as smart watches, fitness trackers, smart sensors, and smart glasses. Low power consumption is a requirement of the processors and the increasingly large embedded SRAMs in such devices. Lowering the operating voltage of these devices makes them low power. However, process variation at lower voltages causes read and write reliability issues in SRAM bitcells. To overcome issues in SRAM reliability, we present a novel, integrated read and write assist scheme with area and power savings as compared to existing state of the art schemes. For write assist, we inject negative bitline bias to raise the gate to source voltage of the bitcell access transistor, improving write margin. For read assist, we lower bitline precharge levels by adding one transistor per bitline column. Area and power savings come from capacitance sharing between the read and write assist circuitry and by precharging bitlines using recycled charged. In our SRAM implementation of the proposed circuit, we found as high as 10% dynamic power savings during bitline precharging. Using negative bitline techniques further reduced power consumption through an approximately 150mV reduction in operating voltage. Depending on the read and write margin requirements, capacitors in the design can be programmable and isolated for flexibility. The SRAM array presented in this paper also utilizes a variety of leakage reduction modes. In terms of area, for a 16384×72m8fb8 memory instance, the area overhead was only 1.7%. SRAMs using the low power, low area overhead assist scheme and the leakage reduction modes can have significant applications in wearable electronics and IoT.","PeriodicalId":385714,"journal":{"name":"2017 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2017-07-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129697636","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Comparative study and optimization of synchronous and asynchronous comparators at near-threshold voltages 近阈值电压下同步与异步比较器的比较研究与优化

2017 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED) Pub Date : 2017-07-24 DOI: 10.1109/ISLPED.2017.8009169

S. Kim, Doyun Kim, Mingoo Seok

引用次数: 15

XNOR-POP: A processing-in-memory architecture for binary Convolutional Neural Networks in Wide-IO2 DRAMs XNOR-POP:一种用于宽io2 dram的二进制卷积神经网络的内存处理架构

2017 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED) Pub Date : 2017-07-24 DOI: 10.1109/ISLPED.2017.8009163

Lei Jiang, Minje Kim, Wujie Wen, Danghui Wang

引用次数: 52

A carbon nanotube transistor based RISC-V processor using pass transistor logic 采用通管逻辑的基于碳纳米管晶体管的RISC-V处理器

2017 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED) Pub Date : 2017-07-24 DOI: 10.1109/ISLPED.2017.8009156

Aporva Amarnath, Siying Feng, S. Pal, T. Ajayi, A. Rovinski, R. Dreslinski

{"title":"A carbon nanotube transistor based RISC-V processor using pass transistor logic","authors":"Aporva Amarnath, Siying Feng, S. Pal, T. Ajayi, A. Rovinski, R. Dreslinski","doi":"10.1109/ISLPED.2017.8009156","DOIUrl":"https://doi.org/10.1109/ISLPED.2017.8009156","url":null,"abstract":"With silicon-based transistors approaching their scaling limits, multiple successor technologies are competing for silicon's place. Due to recent fabrication breakthroughs, one promising alternative is the carbon nanotube field-effect transistor (CNTFET), which uses carbon nanotubes as the channel medium instead of silicon. Although logic gates using CNTFETs have been demonstrated to provide up to an order of magnitude better energy-delay product (EDP) over silicon-based counterparts, system-level design using CNTFETs show significantly smaller EDP improvement because of the critical path of the design, output load capacitance and corresponding drive strengths of gates. In this paper, we address this challenge by exploring various architectural design choices using CNTFET-based pass transistor logic (PTL) and create an energy-efficient RISC-V processor. While silicon-based design traditionally prefers complementary logic over PTL, CNTFETs are ideal candidates for PTL due to their low threshold voltage, low power dissipation, and equal strength p-type and n-type transistors. By utilizing PTL to design modules that lie on the processor's critical path, systems can efficiently exploit CNTFET's potential benefits. Our results show that while a CNTFET RISC-V processor using complementary logic achieves a 2.9× EDP improvement over a silicon design, using PTL along the critical path components in the ALU can boost EDP improvement 5× as well as reduce area by 17% over 16 nm silicon CMOS.","PeriodicalId":385714,"journal":{"name":"2017 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2017-07-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124174458","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

Temporal codes in on-chip interconnects 片上互连中的时间码

2017 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED) Pub Date : 2017-07-24 DOI: 10.1109/ISLPED.2017.8009158

Michael Mishkin, N. Kim, Mikko H. Lipasti

引用次数: 2

Architecting large-scale SRAM arrays with monolithic 3D integration 构建具有单片3D集成的大规模SRAM阵列

2017 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED) Pub Date : 2017-07-24 DOI: 10.1109/ISLPED.2017.8009157

J. Kong, Young-Ho Gong, S. Chung

引用次数: 16

A data remanence based approach to generate 100% stable keys from an SRAM physical unclonable function 基于数据残留的方法，从SRAM物理不可克隆函数生成100%稳定的键

2017 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED) Pub Date : 2017-07-24 DOI: 10.1109/ISLPED.2017.8009192

Muqing Liu, Chen Zhou, Qianying Tang, K. Parhi, C. Kim

{"title":"A data remanence based approach to generate 100% stable keys from an SRAM physical unclonable function","authors":"Muqing Liu, Chen Zhou, Qianying Tang, K. Parhi, C. Kim","doi":"10.1109/ISLPED.2017.8009192","DOIUrl":"https://doi.org/10.1109/ISLPED.2017.8009192","url":null,"abstract":"The start-up value of an SRAM cell is unique, random, and unclonable as it is determined by the inherent process mismatch between transistors. These properties make SRAM an attractive circuit for generating encryption keys. The primary challenge for SRAM based key generation, however, is the poor stability when the circuit is subject to random noise, temperature and voltage changes, and device aging. Temporal majority voting (TMV) and bit masking were used in previous works to identify and store the location of unstable or marginally stable SRAM cells. However, TMV requires a long test time and significant hardware resources. In addition, the number of repetitive power-ups required to find the most stable cells is prohibitively high. To overcome the shortcomings of TMV, we propose a novel data remanence based technique to detect SRAM cells with the highest stability for reliable key generation. This approach requires only two remanence tests: writing ‘1’ (or ‘0’) to the entire array and momentarily shutting down the power until a few cells flip. We exploit the fact that the cells that are easily flipped are the most robust cells when written with the opposite data. The proposed method is more effective in finding the most stable cells in a large SRAM array than a TMV scheme with 1,000 power-up tests. Experimental studies show that the 256-bit key generated from a 512 kbit SRAM using the proposed data remanence method is 100% stable under different temperatures, power ramp up times, and device aging.","PeriodicalId":385714,"journal":{"name":"2017 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2017-07-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133094486","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 24

Enabling efficient fine-grained DRAM activations with interleaved I/O 通过交错I/O实现高效的细粒度DRAM激活

2017 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED) Pub Date : 2017-07-24 DOI: 10.1109/ISLPED.2017.8009201

Chao Zhang, Xiaochen Guo

引用次数: 6