Ming-Hung Chien, Yen-Long Lee, J. Goh, Soon-Jyh Chang
{"title":"一种低功率双电压模式发射机","authors":"Ming-Hung Chien, Yen-Long Lee, J. Goh, Soon-Jyh Chang","doi":"10.1109/ISLPED.2017.8009205","DOIUrl":null,"url":null,"abstract":"This paper presents a novel low power duobinary voltage mode transmitter in 90-nm CMOS process for wireline communication. As a matter of fact, voltage mode transmitters potentially save much more power than current mode transmitters. By adding a medium level, a half supply voltage, to conventional NRZ voltage mode transmitters, duobinary coding can simply be achieved. Post-layout simulation demonstrates the architecture with a new preemphasis method dissipates approximately 16.35 mW from a 1.0 V supply when transmitting 8 Gb/s 1.0 V differential amplitude data with 2-tap pre-emphasis, achieving 2.04 pJ/bit energy efficiency.","PeriodicalId":385714,"journal":{"name":"2017 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED)","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2017-08-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"A low power duobinary voltage mode transmitter\",\"authors\":\"Ming-Hung Chien, Yen-Long Lee, J. Goh, Soon-Jyh Chang\",\"doi\":\"10.1109/ISLPED.2017.8009205\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents a novel low power duobinary voltage mode transmitter in 90-nm CMOS process for wireline communication. As a matter of fact, voltage mode transmitters potentially save much more power than current mode transmitters. By adding a medium level, a half supply voltage, to conventional NRZ voltage mode transmitters, duobinary coding can simply be achieved. Post-layout simulation demonstrates the architecture with a new preemphasis method dissipates approximately 16.35 mW from a 1.0 V supply when transmitting 8 Gb/s 1.0 V differential amplitude data with 2-tap pre-emphasis, achieving 2.04 pJ/bit energy efficiency.\",\"PeriodicalId\":385714,\"journal\":{\"name\":\"2017 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED)\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2017-08-11\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2017 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISLPED.2017.8009205\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2017 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISLPED.2017.8009205","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
This paper presents a novel low power duobinary voltage mode transmitter in 90-nm CMOS process for wireline communication. As a matter of fact, voltage mode transmitters potentially save much more power than current mode transmitters. By adding a medium level, a half supply voltage, to conventional NRZ voltage mode transmitters, duobinary coding can simply be achieved. Post-layout simulation demonstrates the architecture with a new preemphasis method dissipates approximately 16.35 mW from a 1.0 V supply when transmitting 8 Gb/s 1.0 V differential amplitude data with 2-tap pre-emphasis, achieving 2.04 pJ/bit energy efficiency.