2017 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED)最新文献_第2页

CORAL: Coarse-grained reconfigurable architecture for Convolutional Neural Networks CORAL:卷积神经网络的粗粒度可重构架构

2017 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED) Pub Date : 2017-07-24 DOI: 10.1109/ISLPED.2017.8009162

Zhe Yuan, Yongpan Liu, Jinshan Yue, Jinyang Li, Huazhong Yang

引用次数: 11

Monolithic 3D IC designs for low-power deep neural networks targeting speech recognition 针对语音识别的低功耗深度神经网络的单片3D集成电路设计

2017 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED) Pub Date : 2017-07-24 DOI: 10.1109/ISLPED.2017.8009175

Kyungwook Chang, Deepak Kadetotad, Yu Cao, Jae-sun Seo, S. Lim

{"title":"Monolithic 3D IC designs for low-power deep neural networks targeting speech recognition","authors":"Kyungwook Chang, Deepak Kadetotad, Yu Cao, Jae-sun Seo, S. Lim","doi":"10.1109/ISLPED.2017.8009175","DOIUrl":"https://doi.org/10.1109/ISLPED.2017.8009175","url":null,"abstract":"In recent years, deep learning has become widespread for various real-world recognition tasks. In addition to recognition accuracy, energy efficiency is another grand challenge to enable local intelligence in edge devices. In this paper, we investigate the adoption of monolithic 3D IC (M3D) technology for deep learning hardware design, using speech recognition as a test vehicle. M3D has recently proven to be one of the leading contenders to address the power, performance and area (PPA) scaling challenges in advanced technology nodes. Our study encompasses the influence of key parameters in DNN hardware implementations towards energy efficiency, including DNN architectural choices, underlying workloads, and tier partitioning choices in M3D. Our post-layout M3D designs, together with hardware-efficient sparse algorithms, produce power savings beyond what can be achieved using conventional 2D ICs. Experimental results show that M3D offers 22.3% iso-performance power saving, convincingly demonstrating its entitlement as a solution for DNN ASICs. We further present architectural guidelines for M3D DNNs to maximize the power saving.","PeriodicalId":385714,"journal":{"name":"2017 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2017-07-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121648969","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 10

A 32nm, 0.65–10GHz, 0.9/0.3 ps/σ TX/RX jitter single inductor digital fractional-n clock generator for reconfigurable serial I/O 32nm, 0.65-10GHz, 0.9/0.3 ps/σ TX/RX抖动单电感数字分数n时钟发生器，用于可重构串行I/O

2017 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED) Pub Date : 2017-07-24 DOI: 10.1109/ISLPED.2017.8009160

William Y. Li, Hyung Seok Kim, K. Chandrashekar, K. M. Nguyen, A. Ravi

{"title":"A 32nm, 0.65–10GHz, 0.9/0.3 ps/σ TX/RX jitter single inductor digital fractional-n clock generator for reconfigurable serial I/O","authors":"William Y. Li, Hyung Seok Kim, K. Chandrashekar, K. M. Nguyen, A. Ravi","doi":"10.1109/ISLPED.2017.8009160","DOIUrl":"https://doi.org/10.1109/ISLPED.2017.8009160","url":null,"abstract":"In CPU, SOC, GPU, and PC-on-chip, I/O power consumption can be significant. To improve power efficiency, I/O bundles in group of 4, 8, or 16b, should scale their data rate according to the application requirements. However, clocking architecture imposes significant challenges to support different data rate simultaneously. In high bandwidth I/O, LC oscillators are preferred for low jitter, but the limited frequency range confines the data rate tuning. Multiple LC-PLLs are costly in area and power, and sometimes infeasible due to heavily congested I/O area. Worse still, couplings between inductors could lead to PLL pulling closing the sampling eye. In this paper, a reconfigurable 0.65–10GHz digital fractional-n clock generator using a single LC PLL, calibrated 0.75/1.25/1.75 digital fractional post dividers for serial I/O is presented. The architecture enables I/O driven by the same PLL to operate at different data rate, thereby reducing power. In addition, multiple LC-PLLs are replaced by one saving area, power, and coupling between LC oscillators. The PLL incorporates a staggered varactor, wide-tuning VCO, and a hysteretic redundant frequency acquisition for improved temperature stability. The prototype in a 32nm high-k metal gate process has a measured TX/RX jitter of 0.9/0.3 ps/σ and dissipates 36.2mW from 1.05V supply.","PeriodicalId":385714,"journal":{"name":"2017 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2017-07-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121561117","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Exploring sparsity of firing activities and clock gating for energy-efficient recurrent spiking neural processors 高能效循环尖峰神经处理器的发射活动稀疏性与时钟门控研究

2017 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED) Pub Date : 2017-07-24 DOI: 10.1109/ISLPED.2017.8009197

Yu Liu, Yingyezhe Jin, Peng Li

引用次数: 6

A tunable Ultra Low Power inductorless Low Noise Amplifier exploiting body biasing of 28 nm FDSOI technology 一种利用28纳米FDSOI技术体偏置的可调谐超低功率无电感低噪声放大器

2017 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED) Pub Date : 2017-07-24 DOI: 10.1109/ISLPED.2017.8009161

J. Zaini, F. Hameau, T. Taris, D. Morche, P. Audebert, E. Mercier

引用次数: 9

Frequency governors for cloud database OLTP workloads 用于云数据库OLTP工作负载的频率调控器

2017 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED) Pub Date : 2017-07-24 DOI: 10.1109/ISLPED.2017.8009183

Rathijit Sen, A. Halverson

引用次数: 3

Hotspot monitoring and Temperature Estimation with miniature on-chip temperature sensors 用微型片上温度传感器进行热点监测和温度估计

2017 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED) Pub Date : 2017-07-24 DOI: 10.1109/ISLPED.2017.8009191

P. K. Chundi, Yini Zhou, Martha A. Kim, E. Kursun, Mingoo Seok

引用次数: 7

Write-energy-saving ReRAM-based nonvolatile SRAM with redundant bit-write-aware controller for last-level caches 具有冗余位写感知控制器的基于读写节能的非易失SRAM

2017 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED) Pub Date : 2017-07-24 DOI: 10.1109/ISLPED.2017.8009153

Tsai-Kan Chien, L. Chiou, Yi-Sung Tsou, S. Sheu, Pei-Hua Wang, M. Tsai, Chih-I Wu

引用次数: 4

SENIN: An energy-efficient sparse neuromorphic system with on-chip learning 具有片上学习功能的高效稀疏神经形态系统

2017 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED) Pub Date : 2017-07-24 DOI: 10.1109/ISLPED.2017.8009174

Myung-Hoon Choi, Seungkyu Choi, Jaehyeong Sim, L. Kim

引用次数: 2

Online tuning of Dynamic Power Management for efficient execution of interactive workloads 动态电源管理的在线调优，以有效地执行交互式工作负载

2017 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED) Pub Date : 2017-07-01 DOI: 10.1109/ISLPED.2017.8009195

James R. B. Bantock, V. Tenentes, B. Al-Hashimi, G. Merrett

{"title":"Online tuning of Dynamic Power Management for efficient execution of interactive workloads","authors":"James R. B. Bantock, V. Tenentes, B. Al-Hashimi, G. Merrett","doi":"10.1109/ISLPED.2017.8009195","DOIUrl":"https://doi.org/10.1109/ISLPED.2017.8009195","url":null,"abstract":"Modern mobile devices contain powerful Multi-Processor System-on-Chips (MPSoCs) that are performance throttled by Dynamic Power Management (DPM) runtime systems to extend battery lifetime. Applications on mobile devices commonly generate highly interactive workloads, dependent on interaction between the processor cores, peripherals, external resources and the user, such as touch input during web-browsing. Inevitably, a subset of interactive workloads are affected by delays caused by data unavailability, e.g. loss or delay of data packets during voice-over-IP. At the same time, the system is required to respond quickly upon data retrieval to ensure that the user Quality of Experience (QoE) metrics (frame-rate, latency, etc.) are not degraded. Traditionally, operating systems have mitigated this problem with periodic sampling or event-driven approaches. Through experimentation using a mobile MPSoC platform, however, we demonstrate that improving the tuning of DPM parameters for certain interactive user inputs can provide energy savings of up to 21% or QoE improvements of up to 36%, when compared with the traditional approach. To capture these improvements, we propose a dynamic modeling of user input and data resource access times (e.g. mobile network bandwidth and latency) for interactive workloads, which is based on workload profiling and which we refer to herein as inelasticity analysis. The proposed approach is implemented through online tuning of a DPM runtime in the Android operating system and is validated through a Monte Carlo simulation of interactive workloads. In comparison to the default DPM tuning, the proposed approach achieves energy savings of 13% or QoE improvement of 27% or a selectable trade-off, e.g. 9% energy savings and 15% QoE improvement.","PeriodicalId":385714,"journal":{"name":"2017 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2017-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116953845","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4