Charge recycled low power SRAM with integrated write and read assist, for wearable electronics, designed in 7nm FinFET

A recent trend in the electronics industry is the concept of intelligent wearables and the Internet of Things (IoT) such as smart watches, fitness trackers, smart sensors, and smart glasses. Low power consumption is a requirement of the processors and the increasingly large embedded SRAMs in such devices. Lowering the operating voltage of these devices makes them low power. However, process variation at lower voltages causes read and write reliability issues in SRAM bitcells. To overcome issues in SRAM reliability, we present a novel, integrated read and write assist scheme with area and power savings as compared to existing state of the art schemes. For write assist, we inject negative bitline bias to raise the gate to source voltage of the bitcell access transistor, improving write margin. For read assist, we lower bitline precharge levels by adding one transistor per bitline column. Area and power savings come from capacitance sharing between the read and write assist circuitry and by precharging bitlines using recycled charged. In our SRAM implementation of the proposed circuit, we found as high as 10% dynamic power savings during bitline precharging. Using negative bitline techniques further reduced power consumption through an approximately 150mV reduction in operating voltage. Depending on the read and write margin requirements, capacitors in the design can be programmable and isolated for flexibility. The SRAM array presented in this paper also utilizes a variety of leakage reduction modes. In terms of area, for a 16384×72m8fb8 memory instance, the area overhead was only 1.7%. SRAMs using the low power, low area overhead assist scheme and the leakage reduction modes can have significant applications in wearable electronics and IoT.