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Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits最新文献

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A design of transponder IC for highly collision resistive RFID systems 一种用于高抗碰撞RFID系统的应答器IC设计
Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits Pub Date : 2004-11-01 DOI: 10.1109/APASIC.2004.1349527
Y. Fukumizu, M. Nagata, S. Ohno, K. Taki
{"title":"A design of transponder IC for highly collision resistive RFID systems","authors":"Y. Fukumizu, M. Nagata, S. Ohno, K. Taki","doi":"10.1109/APASIC.2004.1349527","DOIUrl":"https://doi.org/10.1109/APASIC.2004.1349527","url":null,"abstract":"The RFID system is attracting attentions in the field of automatic identification. Especially, they need a system that can identify a thousand of tags at a time in practical use. We proposed a communication scheme in combination of time hopping CDMA, CRC error-detecting, and repetition of transmission for error recovery to resolve collision problems by simple circuits. The scheme realizes identification of a thousand in 300 msec with low error rate of 1.214 /spl times/ 10/sup -11/. This paper presents an experimental tag circuit which achieves low power operation of 23.4 /spl mu/W with the core area of 12520 /spl mu/m/sup 2/.","PeriodicalId":375715,"journal":{"name":"Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114251186","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
A PVT-insensitive CMOS output driver with constant slew rate 一种恒摆率的pvt不敏感CMOS输出驱动器
Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits Pub Date : 2004-11-01 DOI: 10.1109/APASIC.2004.1349423
S. Choi, Hong-June Park
{"title":"A PVT-insensitive CMOS output driver with constant slew rate","authors":"S. Choi, Hong-June Park","doi":"10.1109/APASIC.2004.1349423","DOIUrl":"https://doi.org/10.1109/APASIC.2004.1349423","url":null,"abstract":"In this paper, we propose an output driver which has constant slew rate over PVT variation. To make output driver's slew rate to be constant, rising and failing time of pre-driving node of output driver is kept constant by predriver, which has constant pull-up and pull-down path resistance. To make output voltage swing level to be constant, another replica bias circuit was used with CMOS push-pull output driver. HSPICE simulations show that the slew rate is 3.21 V/nS on fast condition and 3.12V/nS on slow condition with 1.4K pre-driver's path resistance. This circuit was implemented with 0.18 /spl mu/m CMOS process.","PeriodicalId":375715,"journal":{"name":"Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits","volume":"446 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122486182","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
A 1.7/spl sim/3.125Gbps clock and data recovery circuit using a gated frequency detector 一个使用门控频率检测器的1.7/spl sim/3.125Gbps时钟和数据恢复电路
Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits Pub Date : 2004-11-01 DOI: 10.1109/APASIC.2004.1349486
Rong-Jyi Yang, Shen-Iuan Liu
{"title":"A 1.7/spl sim/3.125Gbps clock and data recovery circuit using a gated frequency detector","authors":"Rong-Jyi Yang, Shen-Iuan Liu","doi":"10.1109/APASIC.2004.1349486","DOIUrl":"https://doi.org/10.1109/APASIC.2004.1349486","url":null,"abstract":"A fully integrated clock and data recovery (CDR) circuit with the proposed gated frequency detector (GFD) is presented. It has been realized in a standard 0.25-/spl mu/m CMOS technology. The proposed voltage-controlled oscillator (VCO) can achieve wide operation range and small K/sub VCO/ by employing the analog/digital dual loop architecture. It can relax the constraint on choosing the loop parameter to reduce the size of the on-chip capacitor. The proposed GFD will make the frequency lock time fixed and can avoid the harmonic locking problem for wide data rate operations. All measured BERs are less than 10/sup -12/ with the data rate from 1.7Gbps to 3.125Gbps.","PeriodicalId":375715,"journal":{"name":"Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits","volume":"2012 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129213286","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Design and implementation of word-parallel digital associative memories 字并行数字联想存储器的设计与实现
Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits Pub Date : 2004-11-01 DOI: 10.1109/APASIC.2004.1349522
Y. Oike, M. Ikeda, K. Asada
{"title":"Design and implementation of word-parallel digital associative memories","authors":"Y. Oike, M. Ikeda, K. Asada","doi":"10.1109/APASIC.2004.1349522","DOIUrl":"https://doi.org/10.1109/APASIC.2004.1349522","url":null,"abstract":"We present word-parallel digital associative memories with exact Hamming/Manhattan distance computation. A logic-in-memory digital implementation achieves the word-parallel and hierarchical search architecture. It attains a high-speed operation with a large input number, and detects the data close to the input with a fewer number of clocks. The circuit implementation allows unlimited data capacity and achieves a low-voltage operation under 1.0 V for system-on-a-chip applications. The capacity scalability makes it easy to compute a function of Manhattan distance evaluation using thermometer encoding. We have designed 64-bit 32-word associative memories using a 1P5M 0.18 /spl mu/m CMOS process. It achieves 411.5 MHz and 40.0 MHz operations at a supply voltage of 1.8 V and 0.75 V, respectively.","PeriodicalId":375715,"journal":{"name":"Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122016109","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Implementation of a bit-level super-systolic FIR filter 位级超收缩FIR滤波器的实现
Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits Pub Date : 2004-11-01 DOI: 10.1109/APASIC.2004.1349450
Jae-Jin Lee, Gi-Yong Song
{"title":"Implementation of a bit-level super-systolic FIR filter","authors":"Jae-Jin Lee, Gi-Yong Song","doi":"10.1109/APASIC.2004.1349450","DOIUrl":"https://doi.org/10.1109/APASIC.2004.1349450","url":null,"abstract":"High performance computation on a large array of cells has been an important feature of the systolic array. To achieve higher degree of concurrency, it is desirable to make cells of a systolic array themselves a systolic array as well. The structure of a systolic array with its cells consisting of another systolic array is to be called super-systolic array. This paper proposes a bit-level super-systolic FIR filter with an FPGA-based bit-serial semi-systolic multiplier which twists on the shift and add multiplier by positioning upper and lower half of the serial multiplier side by side physically in floorplanning, instead of linearly. The proposed design is better suited to FPGA implementation than bit-level super-systolic FIR filter with a bit-serial systolic multiplier in each cell in terms of hardware complexity, P&R and performance.","PeriodicalId":375715,"journal":{"name":"Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits","volume":"71 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115023932","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
A VLSI architecture of G.SHDSL transceiver 一种g.s shdsl收发器的VLSI结构
Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits Pub Date : 2004-11-01 DOI: 10.1109/APASIC.2004.1349489
S. Yen, Cheng-Shing Wu, M.-T. Shine
{"title":"A VLSI architecture of G.SHDSL transceiver","authors":"S. Yen, Cheng-Shing Wu, M.-T. Shine","doi":"10.1109/APASIC.2004.1349489","DOIUrl":"https://doi.org/10.1109/APASIC.2004.1349489","url":null,"abstract":"This paper presents a design of transceiver architecture specifically for SHDSL system. It integrates programmable karner, trellis encodeddecoder, PSD filter and two adaptive filters of Echo Cancellation (EC) and DFE equalizer (EQ) at the receiver. We propose a method, filtered-X algorithm, to solve the joint EQ and EC adaptation issue with reasonable complexity. Moreover an alldigital timing recovery is adopted in receiver to compensate the clock offset. Fixed-point simulations of the whole system show the proposed architecture is capable for SHDSL system.","PeriodicalId":375715,"journal":{"name":"Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits","volume":"587 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115978598","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
An efficient all-digital built-in self-test for chargepump PLL 一个高效的全数字内置自检电荷泵锁相环
Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits Pub Date : 2004-11-01 DOI: 10.1109/APASIC.2004.1349411
Junseok Han, DongSup Song, Sungho Kang
{"title":"An efficient all-digital built-in self-test for chargepump PLL","authors":"Junseok Han, DongSup Song, Sungho Kang","doi":"10.1109/APASIC.2004.1349411","DOIUrl":"https://doi.org/10.1109/APASIC.2004.1349411","url":null,"abstract":"Analog and mixed-signal testing is becoming an important issue that affects both the time-to-market and product cost of many SoCs. In order to provide an efficient test method for the PLL which is a mixed-signal circuit widely used in most of SoCs, a novel BIST method is developed. It uses the change of phase differences generated by selectively alternating the feedback frequency. This BIST can be easily implemented with several counters and combinational logic gates. The simulation results show higher fault coverage than that of previous test methods. Thus it provides an efficient structural test, which is suitable for a production test in terms of an area overhead, a test accessibility, and test time.","PeriodicalId":375715,"journal":{"name":"Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits","volume":"79 4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126932333","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
T4G: media processor including 3D graphics for mobile set based on configurable processor T4G:基于可配置处理器的移动设备媒体处理器，包括3D图形
Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits Pub Date : 2004-11-01 DOI: 10.1109/APASIC.2004.1349436
T. Takemoto, Y. Takenaka, T. Minagawa, T. Koizumi, Y. Ushijima, N. Yanagida, Y. Ohara, K. Tanaka, Y. Fujita
{"title":"T4G: media processor including 3D graphics for mobile set based on configurable processor","authors":"T. Takemoto, Y. Takenaka, T. Minagawa, T. Koizumi, Y. Ushijima, N. Yanagida, Y. Ohara, K. Tanaka, Y. Fujita","doi":"10.1109/APASIC.2004.1349436","DOIUrl":"https://doi.org/10.1109/APASIC.2004.1349436","url":null,"abstract":"A media processor, \"T4G\", for mobile set is described. 3.5M polygon/sec 3D Graphic engine, 15fps@QVGA MPEG4 codec engine, 2M pixel JPEG codec engine and 20Mbit DRAM are integrated into a single chip with peripheral modules such as Camera I/F and LCDC. The 3D graphics engine was designed based on a Toshiba's configurable processor MeP (Media embedded Processor) to achieve high throughput 3D graphics processing and flexibility. An embedded DRAM provide ultra high memory bandwidth to the 3D graphics engine up to 2Gbyte/sec. This chip is fabricated using 0.13/spl mu/m CMOS technology and integrates 20M transistors and 20Mbit DRAM. It operates at 125MHz and consumes maximum 170mW during 3D graphics operation.","PeriodicalId":375715,"journal":{"name":"Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits","volume":"123 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127045945","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A low-power wide-bandwidth fully differential operational amplifier with current re-using feedforward frequency compensation 一种电流再利用前馈频率补偿的低功率宽带宽全差分运算放大器
Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits Pub Date : 2004-11-01 DOI: 10.1109/APASIC.2004.1349396
Jin-Hong Hwang, C. Yoo
{"title":"A low-power wide-bandwidth fully differential operational amplifier with current re-using feedforward frequency compensation","authors":"Jin-Hong Hwang, C. Yoo","doi":"10.1109/APASIC.2004.1349396","DOIUrl":"https://doi.org/10.1109/APASIC.2004.1349396","url":null,"abstract":"A fully differential operational amplifier (op-amp) is described that simultaneously achieves low power consumption and wide bandwidth by employing current-reusing feedforward compensation scheme. In contrast to the conventional feedfoward frequency compensation, the newly developed scheme re-uses the bias current of the second stage of op-amp and therefore the power consumption is minimized. The op-amp designed in a 0.25/spl mu/m CMOS technology achieves 77dB DC gain, 870MHz unity gain frequency and 56/spl deg/ phase margin for 1pF load capacitance. The op-amp draws 1.8mA from a 2.5V supply.","PeriodicalId":375715,"journal":{"name":"Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits","volume":"86 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131686217","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 18
A new 2.5-V CMOS 10.7-MHz IF circuit 新型2.5 v CMOS 10.7 mhz中频电路
Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits Pub Date : 2004-11-01 DOI: 10.1109/APASIC.2004.1349397
S.C. Li, H. Kao, Ye Wu
{"title":"A new 2.5-V CMOS 10.7-MHz IF circuit","authors":"S.C. Li, H. Kao, Ye Wu","doi":"10.1109/APASIC.2004.1349397","DOIUrl":"https://doi.org/10.1109/APASIC.2004.1349397","url":null,"abstract":"This paper presents a low-voltage low-power 10.7-MHz IF circuit including limiting amplifier and FM/FSK demodulator. The limiting amplifier is implemented by cascaded of seven gain cells. The FM/FSK demodulator employs a new quadrature detector and is composed of an on-chip analog multiplier and an external tank phase shifter. The frequency to voltage conversion gain of the demodulator is 15 mVkHz. The sensitivity of the IF section including demodulator and limiting amplifier is -72 dBm. The current consumption of the proposed IF circuit is 4 mA from a single 2.5 V power supply. It occupies an active area of 580 μm X 1300 μm using 0.25-μm TSMC SP5M CMOS technology.","PeriodicalId":375715,"journal":{"name":"Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131982481","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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