T. Takemoto, Y. Takenaka, T. Minagawa, T. Koizumi, Y. Ushijima, N. Yanagida, Y. Ohara, K. Tanaka, Y. Fujita
{"title":"T4G: media processor including 3D graphics for mobile set based on configurable processor","authors":"T. Takemoto, Y. Takenaka, T. Minagawa, T. Koizumi, Y. Ushijima, N. Yanagida, Y. Ohara, K. Tanaka, Y. Fujita","doi":"10.1109/APASIC.2004.1349436","DOIUrl":null,"url":null,"abstract":"A media processor, \"T4G\", for mobile set is described. 3.5M polygon/sec 3D Graphic engine, 15fps@QVGA MPEG4 codec engine, 2M pixel JPEG codec engine and 20Mbit DRAM are integrated into a single chip with peripheral modules such as Camera I/F and LCDC. The 3D graphics engine was designed based on a Toshiba's configurable processor MeP (Media embedded Processor) to achieve high throughput 3D graphics processing and flexibility. An embedded DRAM provide ultra high memory bandwidth to the 3D graphics engine up to 2Gbyte/sec. This chip is fabricated using 0.13/spl mu/m CMOS technology and integrates 20M transistors and 20Mbit DRAM. It operates at 125MHz and consumes maximum 170mW during 3D graphics operation.","PeriodicalId":375715,"journal":{"name":"Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits","volume":"123 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2004-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/APASIC.2004.1349436","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
Abstract
A media processor, "T4G", for mobile set is described. 3.5M polygon/sec 3D Graphic engine, 15fps@QVGA MPEG4 codec engine, 2M pixel JPEG codec engine and 20Mbit DRAM are integrated into a single chip with peripheral modules such as Camera I/F and LCDC. The 3D graphics engine was designed based on a Toshiba's configurable processor MeP (Media embedded Processor) to achieve high throughput 3D graphics processing and flexibility. An embedded DRAM provide ultra high memory bandwidth to the 3D graphics engine up to 2Gbyte/sec. This chip is fabricated using 0.13/spl mu/m CMOS technology and integrates 20M transistors and 20Mbit DRAM. It operates at 125MHz and consumes maximum 170mW during 3D graphics operation.