Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits最新文献

SoC R&D trend for future digital life 面向未来数字生活的SoC研发趋势

Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits Pub Date : 2005-08-01 DOI: 10.1093/ietele/e88-c.8.1705

Ki Won Lee

引用次数: 4

Interconnect delay aware RTL Verilog bus architecture generation for an SoC 互连延迟感知RTL Verilog总线架构生成的SoC

Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits Pub Date : 2004-11-01 DOI: 10.1109/APASIC.2004.1349441

Kyeong Keol Ryu, A. Talpasanu, V. Mooney, J. Davis

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引用次数: 3

A 2.2 GHz programmable DLL-based frequency multiplier for SOC applications 一个2.2 GHz可编程的基于dll的SOC应用倍频器

Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits Pub Date : 2004-11-01 DOI: 10.1109/APASIC.2004.1349409

Kuo-Hsing Cheng, Shu-Ming Chang, Y. Lo, Shu-Yu Jiang

引用次数: 11

Handshake-wave combined approach with runtime reconfiguration for designing a low latency asynchronous FIFO 握手波结合运行时重构方法设计低延迟异步FIFO

Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits Pub Date : 2004-11-01 DOI: 10.1109/APASIC.2004.1349444

Jeong-Gun Lee, Suk-Jin Kim, Jeong-A Lee, Euiseok Kim, Kiseon Kim

引用次数: 1

Preliminary experiments for power supply noise reduction using stubs 利用存根降低电源噪声的初步实验

Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits Pub Date : 2004-11-01 DOI: 10.1109/APASIC.2004.1349473

T. Nakura, M. Ikeda, K. Asada

引用次数: 9

A phase-locked pulsewidth control loop with programmable duty cycle 具有可编程占空比的锁相脉宽控制环

Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits Pub Date : 2004-11-01 DOI: 10.1109/APASIC.2004.1349412

Kuo-Hsing Cheng, Chia-Wei Su, Chen-Lung Wu, Y. Lo

引用次数: 10

Design of bit manipulation accelerator for communication DSP 通信DSP位处理加速器的设计

Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits Pub Date : 2004-11-01 DOI: 10.1109/APASIC.2004.1349451

S. H. Yoon, S. H. Jeong, M. Sunwoo

引用次数: 0

FPGA implementation of an all-digital T/2-spaced QPSK receiver with Farrow interpolation timing synchronizer and recursive Costas loop 带法罗插值定时同步器和递归Costas环路的全数字T/2间隔QPSK接收机的FPGA实现

Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits Pub Date : 2004-11-01 DOI: 10.1109/APASIC.2004.1349462

Jeng-Kuang Hwang, Cha-Hsing Chu

引用次数: 10

A 32-bit 64-word 9-read, 7-write ported, noise and process variation-tolerant and wide-voltage-range-operative register file using 130 nm technology 采用130纳米技术的32位64字9读7写端口，噪声和工艺变化容忍和宽电压范围操作寄存器文件

Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits Pub Date : 2004-11-01 DOI: 10.1109/APASIC.2004.1349438

Y. Ikeda, M. Sumita

引用次数: 2

Differential transmission line structure for over 10 Gbps signal transmission at global interconnect in Si ULSI 差分传输线结构，用于在Si ULSI全球互连中传输超过10gbps的信号

Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits Pub Date : 2004-11-01 DOI: 10.1109/APASIC.2004.1349516

H. Ito, S. Gomi, H. Sugita, K. Okada, K. Masu

引用次数: 3