Design of bit manipulation accelerator for communication DSP

Abstract

This paper proposes a bit manipulation accelerator (BMA) having application specific instructions, which efficiently supports scrambling, convolutional encoding, puncturing, and interleaving. Conventional DSPs cannot effectively perform bit manipulation functions since they have multiply accumulate (MAC) oriented data paths and word-based functions. However, the proposed accelerator can process efficiently bit manipulation functions using parallel shift and Exclusive-OR (XOR) operations and bit insertion/extraction operations on multiple data. The proposed BMA has been modeled by VHDL and logic synthesized using the SEC 0.18 /spl mu/m standard cell library and the gate count of the BMA is only about 1,700 gates. Performance comparisons show that the number of clock cycles can be reduced about 40% /spl sim/ 80% for scrambling, convolutional encoding and interleaving compared with existing DSPs.