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Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits最新文献

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A CMOS adiabatic logic for low power circuit design 一种用于低功耗电路设计的CMOS绝热逻辑
Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits Pub Date : 2004-11-01 DOI: 10.1109/APASIC.2004.1349493
Hee-sup Song, Jin-Ku Kang
{"title":"A CMOS adiabatic logic for low power circuit design","authors":"Hee-sup Song, Jin-Ku Kang","doi":"10.1109/APASIC.2004.1349493","DOIUrl":"https://doi.org/10.1109/APASIC.2004.1349493","url":null,"abstract":"In this paper, we designed the low power energy recovery circuit using the adiabatic method. The circuit avoids non-abiabatic loss using the output to ground path current control technique by the output signal. Since the circuit operates low frequency (down to 200MHz), we can save the power consumption than other adiabatic circuit. Proposed circuit was designed using TSMC 0.35/spl mu/m CMOS Technology. Simulation result shows that the circuit can be operating up to 400MHz.","PeriodicalId":375715,"journal":{"name":"Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits","volume":"118 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115594575","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
A parallel-pipelined processor for fast fourier transform 用于快速傅里叶变换的并行流水线处理器
Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits Pub Date : 2004-11-01 DOI: 10.1109/APASIC.2004.1349447
Tze-Yun Sung, Chichyang Chen
{"title":"A parallel-pipelined processor for fast fourier transform","authors":"Tze-Yun Sung, Chichyang Chen","doi":"10.1109/APASIC.2004.1349447","DOIUrl":"https://doi.org/10.1109/APASIC.2004.1349447","url":null,"abstract":"In this paper, we proposed a novel VLSI FFT processor based on parallel-pipelined constant geometry algorithm (PCGA). This processor provides constant geometry for each stage of FFT, data reordering is not needed any more. Especially, the PCGA FFT processor increases throughput with increasing number of input points, and sufficiently exploits the advantage of parallel-pipelines computation for digital signal processing applications.","PeriodicalId":375715,"journal":{"name":"Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117106878","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Direct access test scheme for IP core protection IP核保护直接接入测试方案
Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits Pub Date : 2004-11-01 DOI: 10.1109/APASIC.2004.1349467
Yu-Cheng Fan, Hsueh-Yen Yang, H. Tsao
{"title":"Direct access test scheme for IP core protection","authors":"Yu-Cheng Fan, Hsueh-Yen Yang, H. Tsao","doi":"10.1109/APASIC.2004.1349467","DOIUrl":"https://doi.org/10.1109/APASIC.2004.1349467","url":null,"abstract":"In this paper, we propose a novel direct access test scheme for intellectual property (IP) protection. The principles of new watermarking IP protection procedures depend on current IP-based design flow. The core concept is embedding a watermark generator and a test circuit into the IP core at the behavior design level. This method adopts the direct access test scheme. The ownership right is proven during the direct access test process. The watermark does not need to be designed case-by-case according to different IPs. On real designs, our approaches have low hardware overhead, tracking cost, processing time cost, and probability of coincidence. This scheme can protect the soft IP core at various design levels. It is still easy to detect the ownership rights of the IP provider after the chip has been manufactured and packaged Experimental results have demonstrated that the proposed direct access test scheme-based watermarking approaches are indeed practical. The IP provider will be able to trace a company that has engaged in the unauthorized reselling of copies of the IP.","PeriodicalId":375715,"journal":{"name":"Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124669012","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A 14 GHz DLL based low-jitter multi-phase clock generator for low-band ultra-wideband application 一种基于14ghz DLL的低频段超宽带低抖动多相时钟发生器
Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits Pub Date : 2004-11-01 DOI: 10.1109/APASIC.2004.1349487
Tsung-Te Liu, Chorng-Kuang Wang
{"title":"A 14 GHz DLL based low-jitter multi-phase clock generator for low-band ultra-wideband application","authors":"Tsung-Te Liu, Chorng-Kuang Wang","doi":"10.1109/APASIC.2004.1349487","DOIUrl":"https://doi.org/10.1109/APASIC.2004.1349487","url":null,"abstract":"This paper presents the implementation of a low-jitter system clock generator for low-band ultra-wideband (UWB) application based on a wide-range adaptive-bandwidth delay-locked loop (DLL). The false-locking problem commonly along with the wide-range DLL is eliminated by the proposed digital self-correcting loop which also speeds up the lock-in time of the DLL. With self-biased techniques, the proposed DLL adaptively adjusts bandwidth and exhibits optimal jitter transfer characteristic over a wide frequency range and across process, voltage, and temperature (PVT) variations. Fabricated in a 0.18 /spl mu/m CMOS technology, the design achieves an output multiphase sampling clock rate of 1 to 4 GHz and exhibits the maximum input tracking jitter of 12.06 ps (rms) and 88.9 ps (pk-pk) over the operating frequency range from 31.25 to 125 MHz. The prototype occupies an active area of 360 /spl times/ 245 /spl mu/m/sup 2/ and consumes 32 mW from a 1.8-V supply at 125 MHz.","PeriodicalId":375715,"journal":{"name":"Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127977565","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
1.0 Gbps LVDS transceiver design for LCD panels LCD面板1.0 Gbps LVDS收发器设计
Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits Pub Date : 2004-11-01 DOI: 10.1109/APASIC.2004.1349459
Chua-Chin Wang, Jian-Ming Huang, Jih-Fon Huang
{"title":"1.0 Gbps LVDS transceiver design for LCD panels","authors":"Chua-Chin Wang, Jian-Ming Huang, Jih-Fon Huang","doi":"10.1109/APASIC.2004.1349459","DOIUrl":"https://doi.org/10.1109/APASIC.2004.1349459","url":null,"abstract":"LVDS has become a popular choice for high-speed serial links in large-sized display units. This work presents the design and implementation of I/O interface circuits for Gbps operation which is fully complied with the IEEE STD. 1596.3 (LVDS). A step-down voltage regulator is employed to reject the noise coupled in the system power supply. A CMFB (common mode feedback) circuitry is utilized in the transmitter to stabilize the common mode voltage in a predefined range. By contrast, a regenerative circuit which provides a positive feedback loop gain between the preamplifier and the output buffer in the receiver. A typical 0.25 /spl mu/m 1P5M CMOS technology is used to realize the proposed LVDS transceiver. The post-layout simulation reveals that the data rate is 1.0 Gbps at all process corners.","PeriodicalId":375715,"journal":{"name":"Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits","volume":"600 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123165029","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
An ultra-small RFID chip: /spl mu/-chip 一种超小型RFID芯片:/spl μ /-chip
Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits Pub Date : 2004-11-01 DOI: 10.1109/APASIC.2004.1349387
M. Usami
{"title":"An ultra-small RFID chip: /spl mu/-chip","authors":"M. Usami","doi":"10.1109/APASIC.2004.1349387","DOIUrl":"https://doi.org/10.1109/APASIC.2004.1349387","url":null,"abstract":"An ultra-small (0.3 /spl times/ 0.3 /spl times/ 0.06 mm) radiofrequency identification chip, called the /spl mu/-chip, has been developed for use in a wide range of individual recognition applications. The chip is designed to be thin enough to be applied to the paper and paper-like media widely used in retailing to create certificates that have monetary value, as well as to tokens. It was designed and fabricated using 0.18-/spl mu/m standard CMOS technology.","PeriodicalId":375715,"journal":{"name":"Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121316488","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 22
An approach for integration of demodulators for digital broadcasting 一种用于数字广播的解调器集成方法
Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits Pub Date : 2004-11-01 DOI: 10.1109/APASIC.2004.1349517
H. Kobatake, K. Hirano, N. Kuroki, M. Numa, H. Nishida, K. Kawashima, K. Yamamoto
{"title":"An approach for integration of demodulators for digital broadcasting","authors":"H. Kobatake, K. Hirano, N. Kuroki, M. Numa, H. Nishida, K. Kawashima, K. Yamamoto","doi":"10.1109/APASIC.2004.1349517","DOIUrl":"https://doi.org/10.1109/APASIC.2004.1349517","url":null,"abstract":"We propose a method to reduce the circuit size with demodulators for BS digital broadcasting and for terrestrial broadcasting by integrating them. Specifically, we propose an approach for integrating an FIR filter in a BS demodulator, and a carrier filter in a demodulator for terrestrial broadcasting. Experimental results have shown that the proposed approach reduces 17% of the circuit size compared with the sum of each filter.","PeriodicalId":375715,"journal":{"name":"Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits","volume":"74 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123009758","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 2.5Gbps serial-link data transceiver in a 0.35 /spl mu/m digital CMOS technology 采用0.35 /spl mu/m数字CMOS技术的2.5Gbps串行链路数据收发器
Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits Pub Date : 2004-11-01 DOI: 10.1109/APASIC.2004.1349458
Wei-Zen Chen, Meng-Chih Weng
{"title":"A 2.5Gbps serial-link data transceiver in a 0.35 /spl mu/m digital CMOS technology","authors":"Wei-Zen Chen, Meng-Chih Weng","doi":"10.1109/APASIC.2004.1349458","DOIUrl":"https://doi.org/10.1109/APASIC.2004.1349458","url":null,"abstract":"This paper presents the design of a single chip serial link data transceiver. Incorporating with 8 to 1 multiplexer and 1 to 8 demultiplexer, the transceiving data rate ranges from 640 Mbps to 2.56 Gbps. In the transmitter side, a novel precharged type multiplexer is proposed to minimize deterministic jitter. In the receiver side, an oversampling data recovery loop utilizing mixed-signal phase picking scheme is adopted for data resynchronization and demultiplexing. A novel phase interpolator with resistive averaging technique is proposed to generate uniformly distributed sampling phases over wide frequency range, so as to improve bit error rate performance. For data packet size less than 1000 bytes, the tolerated frequency offset between transmitter and receiver is about 1.3 % by a built in elastic buffer. The measured data jitter at the transmitter side after multiplexing is 5.8 ps (rms), and is 43.3 ps (rms) at the receiver side after demultiplexing. The measured bit error rate for 2.5 Gbps data receiving is about 10/sup -10/. Fabricated in a 0.35 /spl mu/m digital CMOS process, this chip occupies 2.9 mm /spl times/ 2.4 mm. The total power consumption is 280 mW under 2V supply.","PeriodicalId":375715,"journal":{"name":"Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits","volume":"134 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126013008","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A 6-bit 500-Ms/s digital self-calibrated pipelined analog-to-digital converter 一个6位500毫秒/秒的数字自校准流水线模数转换器
Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits Pub Date : 2004-11-01 DOI: 10.1109/APASIC.2004.1349417
Yuhu Chen, Tai-Cheng Lee
{"title":"A 6-bit 500-Ms/s digital self-calibrated pipelined analog-to-digital converter","authors":"Yuhu Chen, Tai-Cheng Lee","doi":"10.1109/APASIC.2004.1349417","DOIUrl":"https://doi.org/10.1109/APASIC.2004.1349417","url":null,"abstract":"A 6-bit 500-Ms/s digital self-calibrated pipelined A/D converter is presented. Employing open-loop amplifiers in one bit conversion per stage architecture, the circuit operates in high speed and low power consumption. Using constant-g/sub m/ biasing technique, the open loop amplifier is process-and-temperature insensitive. Comparator offset and full-scale error are removed by digital self-calibrated correction mechanism. Designed by a 0.18-/spl mu/m technology, the A/D converter operates at 500-MHz clock rate while dissipating 47 mW. The FFT simulation result shows that the SNDR is 33.52 dB at 51-MHz input frequency and 500-MSPS conversion rate.","PeriodicalId":375715,"journal":{"name":"Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits","volume":"276 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133918185","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Near field communication chip using PIM for bio MEMS sensors 近场通信芯片采用PIM生物MEMS传感器
Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits Pub Date : 2004-11-01 DOI: 10.1109/APASIC.2004.1349528
K. Okada, T. Yamada, T. Uezono, K. Masu, A. Oki, Y. Horiike
{"title":"Near field communication chip using PIM for bio MEMS sensors","authors":"K. Okada, T. Yamada, T. Uezono, K. Masu, A. Oki, Y. Horiike","doi":"10.1109/APASIC.2004.1349528","DOIUrl":"https://doi.org/10.1109/APASIC.2004.1349528","url":null,"abstract":"This paper presents a small-size wireless communication system for bio MEMS sensors, which uses the near field communication of 13.56MHz with Pulse Interval Modulation (PIM). In simulated result, 16mV of output voltage can be obtained at the outside receiver when coupling factor is 0.1.","PeriodicalId":375715,"journal":{"name":"Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133684879","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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