发布求助
文献互助 智能选刊 最新文献

Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits最新文献

筛选
英文 中文
RZ/NRZ dual-rail decoding scheme to reduce switching activities in asynchronous circuits RZ/NRZ双轨解码方案，以减少异步电路中的交换活动
Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits Pub Date : 2004-11-01 DOI: 10.1109/APASIC.2004.1349468
Won-Chul Lee, Je-Hoon Lee, Kyoung-Rok Cho
{"title":"RZ/NRZ dual-rail decoding scheme to reduce switching activities in asynchronous circuits","authors":"Won-Chul Lee, Je-Hoon Lee, Kyoung-Rok Cho","doi":"10.1109/APASIC.2004.1349468","DOIUrl":"https://doi.org/10.1109/APASIC.2004.1349468","url":null,"abstract":"In this paper, we present a new mixture RZ/NRZ dual-rail transmission method to reduce the power consumption associated with data switching and to overcome the zero switching overhead of the RZ dual-rail decoding scheme. The dual-rail data encoding is useful to detect the completion signal of each module in the asynchronous circuits using the DI delay model. However, the dual-rail scheme gives some disadvantages, large chip area and higher power consumption than single-rail counterparts. The proposed method reduces the switching activities of the circuit significantly introducing NRZ transmission on the one rail, which leads to lower power consumption. We evaluated the proposed RZ/NRZ dual-rail scheme using the ISCAS85 benchmarking circuit. As the results, the proposed circuit shows 25% reduction of the signal transition and the lower power consumption to about 27% than the conventional dual-rail encoding with RZ method, respectively.","PeriodicalId":375715,"journal":{"name":"Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits","volume":"113 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122416523","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
ASIC design of IPSec hardware accelerator for network security 面向网络安全的IPSec硬件加速器的ASIC设计
Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits Pub Date : 2004-11-01 DOI: 10.1109/APASIC.2004.1349439
Chang-Soo Ha, Jong-Hyoung Lee, Duck Soo Leem, Myoung-soo Park, B. Choi
{"title":"ASIC design of IPSec hardware accelerator for network security","authors":"Chang-Soo Ha, Jong-Hyoung Lee, Duck Soo Leem, Myoung-soo Park, B. Choi","doi":"10.1109/APASIC.2004.1349439","DOIUrl":"https://doi.org/10.1109/APASIC.2004.1349439","url":null,"abstract":"This paper describes ASIC design of IPSec hardware accelerator for network security which can execute tunnel-mode AH and ESP algorithm of IPSec protocol suite. The processor supports AES-128/192/256, TDES, HMAC-MD5 and HMAC-SHA-1 algorithm to encrypt and authenticate the packet data and operates as hardware coprocessor to accelerate cryptographic routine of FreeS/WAN software. The IPSec hardware accelerator consists of AMBA interface, 2KB packet memory, parameter registers, global controller, and cryptographic module. It was designed using 0.25/spl mu/m CMOS standard cell library and consists of about 78K gates and 2KB memory. Its throughput of ESPAES128-HMAC-SHA1 operation is approximately 200 Mbps at 125MHz for 120-byte test packet.","PeriodicalId":375715,"journal":{"name":"Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits","volume":"72 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115355423","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 20
A parallel multi-pattern PRBS generator and BER tester for 40/sup +/ Gbps Serdes applications 用于40/sup +/ Gbps Serdes应用的并行多模式PRBS发生器和误码率测试仪
Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits Pub Date : 2004-11-01 DOI: 10.1109/APASIC.2004.1349484
Wei-Zen Chen, Guan-Sheng Huang
{"title":"A parallel multi-pattern PRBS generator and BER tester for 40/sup +/ Gbps Serdes applications","authors":"Wei-Zen Chen, Guan-Sheng Huang","doi":"10.1109/APASIC.2004.1349484","DOIUrl":"https://doi.org/10.1109/APASIC.2004.1349484","url":null,"abstract":"This paper presents the design of a programmable PRBS generator and a BER tester according to CCITT recommendations. Implemented in a parallel feedback configuration, this IC features PRBS generation of the sequences of length 2/sup 7/-1, 2/sup 10/-1, 2/sup 15/-1, 2/sup 23/-1 and 2/sup 31/-1 b for up to 40+Gbps Serdes applications with 1:16 multiplexing and demultiplexing. The mark densities of 1/2, 1/4 and 1/8 for each of the patterns are also selectable. This IC could be used as a low cost substitute for more expensive bit error rate test system. Implemented in a 0.18 /spl mu/m CMOS process, the total power dissipation is 141 mW.","PeriodicalId":375715,"journal":{"name":"Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129055276","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
An 8b 220 MS/s 0.25 /spl mu/m CMOS pipeline ADC with on-chip RC-filter based voltage references 一个8b 220 MS/s 0.25 /spl μ m CMOS流水线ADC，片上rc滤波器为基准电压
Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits Pub Date : 2004-11-01 DOI: 10.1093/ietele/e88-c.4.768
Young-Jae Cho, Hyuen-Hee Bae, Seunghoon Lee
{"title":"An 8b 220 MS/s 0.25 /spl mu/m CMOS pipeline ADC with on-chip RC-filter based voltage references","authors":"Young-Jae Cho, Hyuen-Hee Bae, Seunghoon Lee","doi":"10.1093/ietele/e88-c.4.768","DOIUrl":"https://doi.org/10.1093/ietele/e88-c.4.768","url":null,"abstract":"This work proposes an 8b 220 MS/s 230 mW 3-stage pipeline CMOS ADC with on-chip filters for temperature- and power supply-insensitive voltage references. The proposed RC low-pass filters reduce reference settling time at heavy R & C loads and improve switching noise performance without conventional off-chip bypass capacitors. The prototype ADC fabricated in a 0.25 /spl mu/m CMOS occupies the active die area of 2.25 mm/sup 2/ and shows the measured DNL and INL of maximum 0.43 LSB and 0.82 LSB, respectively. The ADC maintains the SNDR of 43 dB and 41 dB up to the 110 MHz input at 200 MS/s and 220 MS/s, respectively, while the SNDR at the 500 MHz input is degraded as much as only 3 dB than the SNDR at the 110 MHz input.","PeriodicalId":375715,"journal":{"name":"Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits","volume":"140 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127328174","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A DLL-based programmable clock generator using threshold-trigger delay element and circular edge combiner 采用阈值触发延迟元件和圆边合成器的基于dll的可编程时钟发生器
Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits Pub Date : 2004-11-01 DOI: 10.1109/APASIC.2004.1349410
Hong-Yi Huang, Jian-Hong Shen
{"title":"A DLL-based programmable clock generator using threshold-trigger delay element and circular edge combiner","authors":"Hong-Yi Huang, Jian-Hong Shen","doi":"10.1109/APASIC.2004.1349410","DOIUrl":"https://doi.org/10.1109/APASIC.2004.1349410","url":null,"abstract":"In this work, a DLL-based CMOS programmable clock generator is presented. A threshold-trigger delay element obtains better duty cycle and jitter performance without dc power consumption. A programmable edge combiner using circular scheme can operate at 0.8V supply voltage. A clock generator programmed by 1, 2, 3 and 6 is design using a 0.18-um 1p6m CMOS process. The input and output frequency ranges of multiply-by-1/2/3/6 clock generator at 1.8V supply voltage are 138 MHz /spl sim/ 277MHz and 138 MHz /spl sim/ 1.6GHz, respectively.","PeriodicalId":375715,"journal":{"name":"Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114523563","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
A 3.1-10.6 GHz CMOS cascaded two-stage distributed amplifier for ultra-wideband application 用于超宽带应用的3.1-10.6 GHz CMOS级联两级分布式放大器
Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits Pub Date : 2004-11-01 DOI: 10.1109/APASIC.2004.1349477
Kuan-Hung Chen, Chorng-Kuang Wang
{"title":"A 3.1-10.6 GHz CMOS cascaded two-stage distributed amplifier for ultra-wideband application","authors":"Kuan-Hung Chen, Chorng-Kuang Wang","doi":"10.1109/APASIC.2004.1349477","DOIUrl":"https://doi.org/10.1109/APASIC.2004.1349477","url":null,"abstract":"In this paper, a CMOS cascaded two-stage distributed amplifier for ultra-wideband (UWB) application is presented. The circuit using two-stage cascaded topology achieves better gain-bandwidth product performance than conventional CMOS distributed amplifiers. The simulated gain is 18dB with /spl plusmn/1dB gain flatness over 3.1/spl sim/10.6 GHz bands. Input and output are matched to 50/spl Omega/, and the return losses of input and output are below -10dB and -9dB respectively. The power dissipation is 54mW with 1.8V power supply. The circuit was fabricated in 0.18-/spl mu/m 1P6M RF CMOS process.","PeriodicalId":375715,"journal":{"name":"Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115799226","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 36
Hardware architecture design for visual processing: present and future 视觉处理的硬件架构设计:现在与未来
Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits Pub Date : 2004-11-01 DOI: 10.1109/APASIC.2004.1349388
Po-Chih Tseng, Liang-Gee Chen
{"title":"Hardware architecture design for visual processing: present and future","authors":"Po-Chih Tseng, Liang-Gee Chen","doi":"10.1109/APASIC.2004.1349388","DOIUrl":"https://doi.org/10.1109/APASIC.2004.1349388","url":null,"abstract":"This paper presents the present and future trends of hardware architecture design for image and video coding. Fundamental design issues are discussed with particular emphasis on efficient dedicated implementation. Hardware architectures for MPEG-4 video coding and JPEG 2000 still image coding are reviewed as examples, and special approaches exploited to improve efficiency are identified. Further perspectives are also presented to address the challenges of hardware architecture design for future image and video coding.","PeriodicalId":375715,"journal":{"name":"Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127712904","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A novel start-controlled phase/frequency detector for multiphase-output delay-locked loops 一种用于多相输出锁相环的新型启控相位/频率检测器
Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits Pub Date : 2004-11-01 DOI: 10.1109/APASIC.2004.1349408
Po-Jen Huang, Hou-Ming Chen, R. Chang
{"title":"A novel start-controlled phase/frequency detector for multiphase-output delay-locked loops","authors":"Po-Jen Huang, Hou-Ming Chen, R. Chang","doi":"10.1109/APASIC.2004.1349408","DOIUrl":"https://doi.org/10.1109/APASIC.2004.1349408","url":null,"abstract":"In this paper, a novel start-controlled phase/frequency detector (PFD) for multiphase-output delay-locked loops (MODLLs) is presented. In the proposed PFD, the start-controlled circuit is used to provide a precise multiphase-output without the locking problem. The PFD utilizes a new NAND-resetable dynamic DFF so that a shorter reset path is achieved. Thus, lower power consumption and higher speed can be obtained. A MODLL using the proposed start-controlled PFD is post-layout simulated using the TSMC 0.35-/spl mu/m 2P4M CMOS process. The results show that the total delay time between the input and the output of the MODLL is just one clock cycle and all of the delay cells provide precise multiphase-output without false locking or harmonic locking. Compared to the static DFF based start-controlled PFD, the power consumption of the proposed NAND-resetable dynamic DFF based PFD is reduced at least 61%. The power consumption of the proposed start-controlled PFD is 100 /spl mu/W at 2V and 100MHz. The area of the MODLL circuit is 426 /spl mu/m /spl times/ 381 /spl mu/m.","PeriodicalId":375715,"journal":{"name":"Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits","volume":"88 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127780913","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
Reduction of FFT circuit area for OFDM demodulator based on skipping-point representation 基于跳点表示的OFDM解调器FFT电路面积减小
Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits Pub Date : 2004-11-01 DOI: 10.1109/APASIC.2004.1349523
M. Nakanishi, H. Kobatake, N. Kobayashi, N. Kuroki, M. Numa, K. Kawashima, K. Yamamoto
{"title":"Reduction of FFT circuit area for OFDM demodulator based on skipping-point representation","authors":"M. Nakanishi, H. Kobatake, N. Kobayashi, N. Kuroki, M. Numa, K. Kawashima, K. Yamamoto","doi":"10.1109/APASIC.2004.1349523","DOIUrl":"https://doi.org/10.1109/APASIC.2004.1349523","url":null,"abstract":"In order to reduce FFT circuit area in OFDM demodulator for terrestrial digital broadcasting system in Japan, we propose an approach to reduce bit width for operations without performance degradation of the demodulator. The most important point is employing 11-bit skipping-point representation for internal operation in FFT instead of 14-bit fixed-point representation. The assignment of bit-fields that minimizes BER (Bit Error Rate) has been chosen for the 11-bit skipping-point representation: 10 bit for significand, and 1 bit for radix-16 exponent. By reducing the bit width for internal operation from 14 to 11, we can reduce the circuit area by 17.6 % with the complex multipliers, and by 21.4 % with the RAMs used in FFT. In total, the area of the whole FFT circuit has been reduced by 18 %. This result shows the effectiveness of the proposed method.","PeriodicalId":375715,"journal":{"name":"Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127831003","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Symbol detection algorithm and implementation results for space-frequency OFDM transmit diversity scheme 空频OFDM发射分集方案的符号检测算法及实现结果
Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits Pub Date : 2004-11-01 DOI: 10.1109/APASIC.2004.1349485
Yunho Jung, Jaeseok Kim
{"title":"Symbol detection algorithm and implementation results for space-frequency OFDM transmit diversity scheme","authors":"Yunho Jung, Jaeseok Kim","doi":"10.1109/APASIC.2004.1349485","DOIUrl":"https://doi.org/10.1109/APASIC.2004.1349485","url":null,"abstract":"In this paper, we propose two efficient symbol detection algorithms for space-frequency OFDM (SF-OFDM) transmit diversity scheme. When the number of sub-carriers in SF-OFDM scheme is small, the interference between adjacent sub-carriers is generated. The proposed algorithms eliminate this interference in parallel or sequential manner and obtain a considerable performance improvement over the conventional detection algorithm. The bit error rate (BER) performance of the proposed detection algorithms was evaluated by the simulation. In the case of 2 transmit and 2 receive antennas, at BER=10/sup -4/ the proposed algorithms obtain about 3 dB gain. In the results of logic synthesis using 0.35 /spl mu/m CMOS technology, the proposed SF-OFDM-PIC and SF-OFDM-SIC symbol detectors are composed of 28K and 26K logic gates, respectively. Since the proposed algorithms cancel the interference caused by the small number of sub-carriers and provide an excellent diversity advantage, SF-OFDM scheme with the proposed algorithms can be a good solution for the systems with the small number of sub-carriers such as wireless LANs.","PeriodicalId":375715,"journal":{"name":"Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits","volume":"43 3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122730447","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
首页 上一页 下一页 尾页
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整，为了账户安全，请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
请完成安全验证×
相关产品
×
本文献相关产品
联系我们：info@booksci.cn Book学术提供免费学术资源搜索服务，方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号：604180095
Book学术官方微信
小红书