A DLL-based programmable clock generator using threshold-trigger delay element and circular edge combiner

Abstract

In this work, a DLL-based CMOS programmable clock generator is presented. A threshold-trigger delay element obtains better duty cycle and jitter performance without dc power consumption. A programmable edge combiner using circular scheme can operate at 0.8V supply voltage. A clock generator programmed by 1, 2, 3 and 6 is design using a 0.18-um 1p6m CMOS process. The input and output frequency ranges of multiply-by-1/2/3/6 clock generator at 1.8V supply voltage are 138 MHz /spl sim/ 277MHz and 138 MHz /spl sim/ 1.6GHz, respectively.