Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits最新文献_第10页

A four transistor CMOS active pixel sensor with high dynamic range operation 具有高动态范围操作的四晶体管CMOS有源像素传感器

Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits Pub Date : 2004-11-01 DOI: 10.1109/APASIC.2004.1349425

Che-I Lin, Cheng-Hsiao Lai, Y. King

引用次数: 15

Three-dimensional round-robin scheduler for advanced input queuing switches 三维轮循调度先进的输入队列开关

Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits Pub Date : 2004-11-01 DOI: 10.1109/APASIC.2004.1349469

G. Jeong, B. Lee

引用次数: 0

A parallel flop synchronizer for bridging asynchronous clock domains 用于桥接异步时钟域的并行触发器同步器

Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits Pub Date : 2004-11-01 DOI: 10.1109/APASIC.2004.1349443

Suk-Jin Kim, Jeong-Gun Lee, Kiseon Kim

引用次数: 6

A new RTL debugging methodology in FPGA-based verification platform 一种基于fpga验证平台的RTL调试方法

Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits Pub Date : 2004-11-01 DOI: 10.1109/APASIC.2004.1349442

Sangjun Yang, H. Shim, Woo-Seung Yang, C. Kyung

引用次数: 18

A fast and power-saving self-timed Manchester carry-bypass adder for Booth multiplier-accumulator design 一种用于布斯乘法器-蓄能器设计的快速省电的自定时曼彻斯特载波旁路加法器

Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits Pub Date : 2004-11-01 DOI: 10.1109/APASIC.2004.1349402

I-Chyn Wey, Hwang-Cherng Chow, You-Gang Chen, A. Wen

引用次数: 1

A low power 5Gb/s transimpedance amplifier with dual feedback technique 采用双反馈技术的低功耗5Gb/s跨阻放大器

Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits Pub Date : 2004-11-01 DOI: 10.1109/APASIC.2004.1349479

I-Hsin Wang, Chung-Shun Liu, Shen-Iuan Liu

引用次数: 2

A dual-band IEEE 802.11a/b/g receiver front-end using half-IF and dual-conversion 采用半中频和双转换的双频IEEE 802.11a/b/g接收机前端

Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits Pub Date : 2004-11-01 DOI: 10.1109/APASIC.2004.1349499

Chun-Chih Hou, C. Chang, Chorng-Kuang Wang

引用次数: 2

Design and implementation of a routing switch for on-chip interconnection networks 片上互连网络路由交换机的设计与实现

Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits Pub Date : 2004-11-01 DOI: 10.1109/APASIC.2004.1349507

Hsin-Chou Chi, Jia-Hung Chen

{"title":"Design and implementation of a routing switch for on-chip interconnection networks","authors":"Hsin-Chou Chi, Jia-Hung Chen","doi":"10.1109/APASIC.2004.1349507","DOIUrl":"https://doi.org/10.1109/APASIC.2004.1349507","url":null,"abstract":"One of the major challenges of system-on-chip (SoC) designs is the communication architecture between heterogeneous components possessing different characteristics. Most of the communication architectures for current SoC designs are based on buses. However, the bus architecture has its inherent limitations. A packet-switched network which delivers messages between communicating components has been proposed as the solution for next-generation SoC Such on-chip interconnection networks provide a chip-level communication infrastructure. In this paper, we present the design and implementation of a routing switch which is the key component for on-chip interconnection networks with mesh or torus topologies. In our design, separate buffers and lookahead routing are employed to effectively solve the blocking problems of packets in buffers. Our simulations show that the on-chip interconnection network with such routing switches outperforms that with conventional switches. We have implemented our switch in 0.25/spl mu/m technology with cell-based design. An initial version of the implementation of the switch can be run at approximately 100MHz.","PeriodicalId":375715,"journal":{"name":"Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131826100","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 12

5 GHz SiGe front-end components for WLAN applications 用于WLAN应用的5 GHz SiGe前端组件

Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits Pub Date : 2004-11-01 DOI: 10.1109/APASIC.2004.1349498

N. Song, Dohyong Kim, J. Burm

引用次数: 2

Arbitration latency analysis of the shared channel architecture for high performance multi-master SoC 高性能多主SoC共享信道架构的仲裁延迟分析

Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits Pub Date : 2004-11-01 DOI: 10.1109/APASIC.2004.1349506

Jisuhn Suh, H. Yoo

{"title":"Arbitration latency analysis of the shared channel architecture for high performance multi-master SoC","authors":"Jisuhn Suh, H. Yoo","doi":"10.1109/APASIC.2004.1349506","DOIUrl":"https://doi.org/10.1109/APASIC.2004.1349506","url":null,"abstract":"We propose new analysis method to estimate the traffic performance of communication channel for system-on-chip (SoC). We define the channel utilization ratio, and we analyze the traffic performance of multi-master system-onchip on shared channel architecture by measure of the arbitration latency. This method is efficient to evaluate the traffic characteristics of the shared channel architecture. And this results offer the methods to optimize the parameter of the components to achieve high performance channel. To verify the efficiency of this method, we experiment the latency of single shared channel architecture by various conditions of components composing SoC. We simulated the effect of number of masters and 2 types of arbitration algorithm by using defined channel utilization ratio. In this analysis, it is found that the arbitration latency increases with the number of masters and channel utilization ratio. The arbitration algorithm affects the arbitration latency according to the number of masters. The throughput of data transaction is proportional to channel utilization ratio.","PeriodicalId":375715,"journal":{"name":"Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126497561","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4