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Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits最新文献

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A single-chip CMOS single-conversion tunable low-IF receiver 单片CMOS单转换可调谐低中频接收器
Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits Pub Date : 2004-11-01 DOI: 10.1109/APASIC.2004.1349399
Chia-Pei Chen, S.C. Li, Hong-Sing Kao, Chung-Chih Su, Kuei-Ann Wen
{"title":"A single-chip CMOS single-conversion tunable low-IF receiver","authors":"Chia-Pei Chen, S.C. Li, Hong-Sing Kao, Chung-Chih Su, Kuei-Ann Wen","doi":"10.1109/APASIC.2004.1349399","DOIUrl":"https://doi.org/10.1109/APASIC.2004.1349399","url":null,"abstract":"0.25-μm single-chip CMOS single -conversion tunable low-IF receiver operated in the 902-928 MHz ISM band is proposed. A new 10.7-MHz IF section including a limiting amplifier and FMlFSK demodulator is designed. The frequency to voltage D conversion gain of the demodulator is 15 mV/kHz. The sensitivity of the IF section including demodulator and limiting amplifier is -72 dBm. With on-chip tunable components in low power LNA and LC-tank VCO circuit, the receiver measures a RF gain of 15dB at 915-MHz, sensitivity of -80dBm at 0.1% BER, llP3 of -9dBm, and NF of 5dB with current consumption of 33mA and a chip area of 2450μ x 2450μm.","PeriodicalId":375715,"journal":{"name":"Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits","volume":"181 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122084695","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 1.2V, 18mW, 10Gb/s SiGe transimpedance amplifier 一个1.2V, 18mW, 10Gb/s SiGe跨阻放大器
Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits Pub Date : 2004-11-01 DOI: 10.1109/APASIC.2004.1349478
Chihun Lee, Chia-Hsin Wu, Shen-Iuan Liu
{"title":"A 1.2V, 18mW, 10Gb/s SiGe transimpedance amplifier","authors":"Chihun Lee, Chia-Hsin Wu, Shen-Iuan Liu","doi":"10.1109/APASIC.2004.1349478","DOIUrl":"https://doi.org/10.1109/APASIC.2004.1349478","url":null,"abstract":"To the authors' knowledge, the first 1.2V, 18mW, 10Gb/s SiGe transimpedance amplifier (TIA) is presented here. It has been realized in a 0.35 /spl mu/m SiGe process and its area is 0.45mm/sup 2/ with pads. Employing inductive series and shunt peaking techniques, the proposed TIA can achieve a transimpedance gain of 61.6dB/spl Omega/ and the bandwidth of 7.4GHz, while dissipating only 18mW with 1.2V supply. With an equivalent photodiode capacitance of 0.15pF, this TIA shows the input referred noise current density of 22pA//spl radic/Hz.","PeriodicalId":375715,"journal":{"name":"Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121077471","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Simultaneous current-mode bidirectional signaling for on-chip interconnection 用于片上互连的同时电流模式双向信令
Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits Pub Date : 2004-11-01 DOI: 10.1109/APASIC.2004.1349504
Hong-Yi Huang, Ching-Chieh Wu, Shih-Lun Chen
{"title":"Simultaneous current-mode bidirectional signaling for on-chip interconnection","authors":"Hong-Yi Huang, Ching-Chieh Wu, Shih-Lun Chen","doi":"10.1109/APASIC.2004.1349504","DOIUrl":"https://doi.org/10.1109/APASIC.2004.1349504","url":null,"abstract":"This work presents on-chip bidirectional signaling scheme. The current signals are transmitted bidirectionally on the interconnection to double the data rate. The voltage swing on the wire is reduced so that the proposed scheme consumes less power at higher data rate. Using 0.18 /spl mu/m device models for simulation, the results show that the proposed scheme has a 40% power reduction than conventional driver. It also performs higher data rate at an extension of wire length.","PeriodicalId":375715,"journal":{"name":"Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits","volume":"205 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123256940","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Low-jitter transmission code for 4-PAM signaling in serial links 串行链路中4-PAM信令的低抖动传输代码
Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits Pub Date : 2004-11-01 DOI: 10.1109/APASIC.2004.1349488
Hsiao-Yun Chen, Chih-Hsien Lin, S. Jou
{"title":"Low-jitter transmission code for 4-PAM signaling in serial links","authors":"Hsiao-Yun Chen, Chih-Hsien Lin, S. Jou","doi":"10.1109/APASIC.2004.1349488","DOIUrl":"https://doi.org/10.1109/APASIC.2004.1349488","url":null,"abstract":"In this paper, we propose a new low-jitter transmission code for 4-PAM signaling in serial links. It is \"8B/10B like code\" which preserves all good properties of the 8B/10B code, such as DC balanced of the serial data and guaranteed enough transitions in the symbol stream for clock recovery. Further, it is effective to reduce the jitter of timing recovery and consumes half the bandwidth to transmit in 4-PAM. The design results using TSMC 0.25 /spl mu/m process shows that it can reduce the jitter of the transition time by /spl plusmn/ 25%. The operation speed of the 8B/10B like encoder/decoder is 500 MHz with 16-bit inputs (8 Gbps) and 476 MHz with 16-bit outputs (7.6 Gbps).","PeriodicalId":375715,"journal":{"name":"Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits","volume":"73 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129916224","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A new output buffer for 3.3-V PCI-X application in a 0.13-/spl mu/m 1/2.5-V CMOS process 在0.13-/spl mu/m 1/2.5 v CMOS工艺中用于3.3 v PCI-X应用的新型输出缓冲器
Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits Pub Date : 2004-11-01 DOI: 10.1109/APASIC.2004.1349422
Shih-Lun Chen, M. Ker
{"title":"A new output buffer for 3.3-V PCI-X application in a 0.13-/spl mu/m 1/2.5-V CMOS process","authors":"Shih-Lun Chen, M. Ker","doi":"10.1109/APASIC.2004.1349422","DOIUrl":"https://doi.org/10.1109/APASIC.2004.1349422","url":null,"abstract":"An output buffer with low-voltage devices to driver high-voltage signals for PCI-X applications is proposed in this paper. Because PCI-X is a 3.3-V interface, the high-voltage gate-oxide stress is a serious problem to design PCI-X I/O circuits in a 0.13-/spl mu/m 1/2.5-V CMOS process. The simulation results show that the proposed output buffer can be operated at 133 MHz without causing high-voltage gate-oxide stress problem in the 3.3-V PCI-X interface. Besides, a level converter with only I-V and 2.5-V devices that can converter 0/1-V voltage swing to 1/3.3-V voltage swing is also proposed in this paper. The testchip to verify this new proposed output buffer is now under fabrication. The measured results will be shown in the presentation.","PeriodicalId":375715,"journal":{"name":"Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits","volume":"67 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129925104","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
A DSP engine for an extensible media embedded processor 用于可扩展媒体嵌入式处理器的DSP引擎
Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits Pub Date : 2004-11-01 DOI: 10.1109/APASIC.2004.1349437
T. Furusawa, I. Katayama, Y. Arai, S. Inoue, M. Matsui, M. Nishikawa, T. Yoshimoto
{"title":"A DSP engine for an extensible media embedded processor","authors":"T. Furusawa, I. Katayama, Y. Arai, S. Inoue, M. Matsui, M. Nishikawa, T. Yoshimoto","doi":"10.1109/APASIC.2004.1349437","DOIUrl":"https://doi.org/10.1109/APASIC.2004.1349437","url":null,"abstract":"An extension interface for a configurable processor enabling implementation of an application specific programmable DSP is described. A DSP engine for mobile applications with 32-bit dual MAC architecture based on the extension was designed. The engine can also run separately as stand-alone processor decoupled with the configurable CPU core. A test chip was successfully fabricated using 0.13/spl mu/m CMOS technology and has measured 0.23 mW/MHz for random logic of the engine and the core.","PeriodicalId":375715,"journal":{"name":"Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130055010","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A CMOS VCO for 1V, 1GHz PLL applications 用于1V, 1GHz锁相环应用的CMOS压控振荡器
Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits Pub Date : 2004-11-01 DOI: 10.1109/APASIC.2004.1349433
Kuo-Hsing Cheng, Ching-Wen Lai, Y. Lo
{"title":"A CMOS VCO for 1V, 1GHz PLL applications","authors":"Kuo-Hsing Cheng, Ching-Wen Lai, Y. Lo","doi":"10.1109/APASIC.2004.1349433","DOIUrl":"https://doi.org/10.1109/APASIC.2004.1349433","url":null,"abstract":"This paper describes a 1V, 1GHz low-noise phase locked-loop (PLL) using a noise-rejected voltage-controlled ring oscillator (VCO). In order to improve the power consumption and oscillation frequency of the PLL, we design the VCO with a new structure of the delay cell. This VCO consists of four-stage fully differential delay cells with the pre-charged scheme that can obtain the characteristics of high speed and low voltage operation. And the bias generator circuit can increase the tuning range and tuning linearity of VCO. The HSPICE simulation results are based upon TSMC 0.18 /spl mu/m 1P6M N-well CMOS process. The simulation results show that the VCO can operate from 50 to 1100 MHz, and when the input control voltage is 0.6V, the oscillation frequency is 1GHz. The power consumption of the PLL is 1.092mW at a supply voltage of 1V.","PeriodicalId":375715,"journal":{"name":"Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114210199","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 16
A novel implementation of cost-effective parallel-pipelined 8x8 DCT processor 一种经济高效的并行流水线8x8 DCT处理器的新实现
Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits Pub Date : 2004-11-01 DOI: 10.1109/APASIC.2004.1349449
Tze-Yun Sung, Y. Sung
{"title":"A novel implementation of cost-effective parallel-pipelined 8x8 DCT processor","authors":"Tze-Yun Sung, Y. Sung","doi":"10.1109/APASIC.2004.1349449","DOIUrl":"https://doi.org/10.1109/APASIC.2004.1349449","url":null,"abstract":", Abstract the periodicity and symtr ‘-qperties, and 1 close to the Loeve transform 2-D Discrete Cosine Transform (DCT) applies i therefore the DCT can r / on image compression and saves more memories. In this paper, we propose a parallel-pipelined architecture to implement a 8x 8 DCT processor. The chip of 8 x 8 DCT processor is fabricated in a 0.25 ,U m CMOS, double-metal technology. The core size is 1.0xl.0mm2 and contains about 85K transistors, and the power dissipation is 60mW at computation the clock rate of 400MHz. All control signals are","PeriodicalId":375715,"journal":{"name":"Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134191455","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Multiplierless multirate decimator/interpolator module generator 无乘法器多速率抽取/插值模块生成器
Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits Pub Date : 2004-11-01 DOI: 10.1109/APASIC.2004.1349404
S. Jou, Kai-Yuan Jheng, Hsiao-Yun Chen, A. Wu
{"title":"Multiplierless multirate decimator/interpolator module generator","authors":"S. Jou, Kai-Yuan Jheng, Hsiao-Yun Chen, A. Wu","doi":"10.1109/APASIC.2004.1349404","DOIUrl":"https://doi.org/10.1109/APASIC.2004.1349404","url":null,"abstract":"A module generator, which can automate the process of designing high-speed low-complexity multistage multirate decimator/interpolator, is presented. The generator exploit architectural symmetries in linear phase filters and multistage multirate interpolated FIR filter design methodology for low complexity. In addition, the polyphase representation is used to decompose the filter into subfilters. The resulting filters utilize canonic signed digit (CSD) multipliers, a transposed direct form structure, and carry-save addition for high speed. A filter design example with TSMC 0.25 /spl mu/m standard cell for 64-QAM baseband demodulator shows that the area is reduced by 39% for low-complexity applications. Moreover, for high-speed application, the chip can operate at 714MHz. Finally, a designed decimator which is used in the CDMA cellular shows that the area is reduced by 70% as compared with conventional approach.","PeriodicalId":375715,"journal":{"name":"Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits","volume":"381 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133939064","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 23
Low-power design for real-time image segmentation LSI and compact digital CMOS implementation 低功耗设计的实时图像分割LSI和紧凑的数字CMOS实现
Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits Pub Date : 2004-11-01 DOI: 10.1109/APASIC.2004.1349524
O. Kiriyama, T. Morimoto, H. Adachi, Y. Harada, T. Koide, H. Mattausch
{"title":"Low-power design for real-time image segmentation LSI and compact digital CMOS implementation","authors":"O. Kiriyama, T. Morimoto, H. Adachi, Y. Harada, T. Koide, H. Mattausch","doi":"10.1109/APASIC.2004.1349524","DOIUrl":"https://doi.org/10.1109/APASIC.2004.1349524","url":null,"abstract":"We present a low-power design for real-time digital image segmentation LSI. We design the CMOS test-chip in a 0.35 /spl mu/m 2-Poly 3-Metal CMOS technology, based on a boundary active only architecture. The design area for 41 /spl times/ 31 pixels is 51.1mm/sup 2/ and the integration density is 26.5pixel/mm/sup 2/. From the circuit simulations at 3.3V supply voltage and 10MHz clock frequency, we obtain a power dissipation of 21.8mW and an image segmentation time of 23/spl mu/sec.","PeriodicalId":375715,"journal":{"name":"Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits","volume":"82 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132791340","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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