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Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits最新文献

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Design of LCD driver IP for SOC applications 用于SOC应用的LCD驱动IP设计
Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits Pub Date : 2004-11-01 DOI: 10.1109/APASIC.2004.1349405
Yu-Jung Huang, Chih-Feng Liu, Shao-Pin Chang, Feng-Yuan Chuang, Chang-Chan Chen
{"title":"Design of LCD driver IP for SOC applications","authors":"Yu-Jung Huang, Chih-Feng Liu, Shao-Pin Chang, Feng-Yuan Chuang, Chang-Chan Chen","doi":"10.1109/APASIC.2004.1349405","DOIUrl":"https://doi.org/10.1109/APASIC.2004.1349405","url":null,"abstract":"This paper describes a scheme for the integration of a LCD driver IP embedded within an ARM-based system-on-chip platform. The LCD driver IP with dot matrix scalable capability can interface to AMBA on chip bus is implemented by hardware description language as a RTL design. The wrapper architecture for AMBA interface is proposed The advantages of the proposed design are easy modification of the common and segment output lines, increasing flexibility for various types of LCD panels with scalable architecture. In our study, the proposed module was verified in ARM AMRA University Kit (AUK) environment.","PeriodicalId":375715,"journal":{"name":"Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits","volume":"182 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122094738","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
SysteMorph prototyping on DAP/DNA 基于DAP/DNA的系统形态原型
Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits Pub Date : 2004-11-01 DOI: 10.1109/APASIC.2004.1349519
Makoto Yoshida, '. TakeshiSOGA, Norifurni, Kazuaki Murakami, Fukuoka Industly
{"title":"SysteMorph prototyping on DAP/DNA","authors":"Makoto Yoshida, '. TakeshiSOGA, Norifurni, Kazuaki Murakami, Fukuoka Industly","doi":"10.1109/APASIC.2004.1349519","DOIUrl":"https://doi.org/10.1109/APASIC.2004.1349519","url":null,"abstract":"Dynamic optimization for software and hardware is gaining attention of computer system researchers. We are researching Systemorph technology. SysteMorph is a dynamic optimization technology proposed by Kyushu University. In this Paper, we discuss SysteMorph prototyping using DAP/DNA to evaluate Systemorph technology.","PeriodicalId":375715,"journal":{"name":"Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits","volume":"138 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123628252","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A low-complexity method for distributed clocking on digital ASICs 一种低复杂度的数字集成电路分布式时钟方法
Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits Pub Date : 2004-11-01 DOI: 10.1109/APASIC.2004.1349492
T. Olsson, P. Nilsson
{"title":"A low-complexity method for distributed clocking on digital ASICs","authors":"T. Olsson, P. Nilsson","doi":"10.1109/APASIC.2004.1349492","DOIUrl":"https://doi.org/10.1109/APASIC.2004.1349492","url":null,"abstract":"A low-complexity method using synchronous wrappers is proposed to simplify communication between modules using unsynchronized clocks. To test the method, it is implemented together with a divider and an FFT co-processor. The divider with synchronous wrapper and local clock generator, delivering a 500 MHz clock, is synthesized and verified using post-synthesis simulations for a 0.18 /spl mu/m 1.8 V CMOS technology. A complete description of the wrapper in synthesizable VHDL-code including local a local clock generator makes the method portable between technologies.","PeriodicalId":375715,"journal":{"name":"Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123853911","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A low phase noise wide tuning range CMOS quadrature VCO using cascade topology 采用级联拓扑的低相位噪声宽调谐范围CMOS正交压控振荡器
Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits Pub Date : 2004-11-01 DOI: 10.1109/APASIC.2004.1349430
Chao-Shiun Wang, Shiau-Wen Kao, Po-Chiun Huang
{"title":"A low phase noise wide tuning range CMOS quadrature VCO using cascade topology","authors":"Chao-Shiun Wang, Shiau-Wen Kao, Po-Chiun Huang","doi":"10.1109/APASIC.2004.1349430","DOIUrl":"https://doi.org/10.1109/APASIC.2004.1349430","url":null,"abstract":"A new fully integrated 2.4GHz CMOS quadrature voltage control oscillator (VCO) is presented. It achieves low phase noise at quadrature outputs using the proposed cascade coupling topology. Digitally-controlled capacitor bank is designed for wide tuning range from 2.4 to 2.9GHz. By a standard 0.25 /spl mu/m single-poly CMOS process with thick top metal, total power consumption of two VCO cores and buffers for generating quadrature signal are 6mA and 12mA respectively. Measured phase noise at 1MHz offset from the center frequency is -114dbc/Hz.","PeriodicalId":375715,"journal":{"name":"Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits","volume":"116 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124217070","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Design of a new RF micromixer with low power and high performance in 0.25/spl mu/m CMOS technology 基于0.25/spl mu/m CMOS技术的低功耗高性能射频微混频器的设计
Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits Pub Date : 2004-11-01 DOI: 10.1109/APASIC.2004.1349431
Kuo-Hua Cheng, Eing-Tsang La, C. Jou
{"title":"Design of a new RF micromixer with low power and high performance in 0.25/spl mu/m CMOS technology","authors":"Kuo-Hua Cheng, Eing-Tsang La, C. Jou","doi":"10.1109/APASIC.2004.1349431","DOIUrl":"https://doi.org/10.1109/APASIC.2004.1349431","url":null,"abstract":"A New CMOS radio-frequency (W) Micromixer has been designed and presented in this paper. source degenerat mdamental limits to the This mixer is derived from the basic micromixer. It has","PeriodicalId":375715,"journal":{"name":"Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130337520","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Four-channel transimpedance amplifier array in a 0.35/spl mu/m CMOS technology for parallel optical interconnects 采用0.35/spl mu/m CMOS技术的四通道透阻放大器阵列，用于并行光互连
Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits Pub Date : 2004-11-01 DOI: 10.1109/APASIC.2004.1349480
T. Hen, Jong-Back Seo, A. Kahng, Sang-Bock Cho, Sujeong Sim, Sung Min Park
{"title":"Four-channel transimpedance amplifier array in a 0.35/spl mu/m CMOS technology for parallel optical interconnects","authors":"T. Hen, Jong-Back Seo, A. Kahng, Sang-Bock Cho, Sujeong Sim, Sung Min Park","doi":"10.1109/APASIC.2004.1349480","DOIUrl":"https://doi.org/10.1109/APASIC.2004.1349480","url":null,"abstract":"A four-channel transimpedance amplifier array is realized in a 0.35μm standard CMOS technology. The amplifier in each channel incorporates the fully differential regulatedcascode configuration, achieving the transimpedance gain of 59.3dBΩ, the -3dB bandwidth of 2.45GHz for 0.5pF photodiode capacitance, and the average noise current spectral density of 16 pA/Hz. The TIA array dissipated the power consumption of 92mW in total from a single 2.5V supply. The whole chip occupies the area of 2.5x1mm2.","PeriodicalId":375715,"journal":{"name":"Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130001333","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Design and optimization of CMOS current mode logic dividers CMOS电流模逻辑分压器的设计与优化
Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits Pub Date : 2004-11-01 DOI: 10.1109/APASIC.2004.1349525
A. Shinmyo, M. Hashimoto, H. Onodera
{"title":"Design and optimization of CMOS current mode logic dividers","authors":"A. Shinmyo, M. Hashimoto, H. Onodera","doi":"10.1109/APASIC.2004.1349525","DOIUrl":"https://doi.org/10.1109/APASIC.2004.1349525","url":null,"abstract":"We designed and measured a high-speed CML divider in a 0.18 /spl mu/m CMOS process. The fabricated chip operates at up to 10GHz with power consumption of 8.6mW. From a small-signal equivalent circuit model, we derive an analytical performance model that gives the relationship among maximum operation frequency, gate width and load resistance. We also discuss the design optimization based on the derived performance model.","PeriodicalId":375715,"journal":{"name":"Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129800530","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
A technology migration method using rectangle-based layout conversion 一种基于矩形布局转换的技术迁移方法
Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits Pub Date : 2004-11-01 DOI: 10.1109/APASIC.2004.1349470
Yong-seok Choi, Ik-Jae Chun, Bogwan Kim, Hyunchul Shin
{"title":"A technology migration method using rectangle-based layout conversion","authors":"Yong-seok Choi, Ik-Jae Chun, Bogwan Kim, Hyunchul Shin","doi":"10.1109/APASIC.2004.1349470","DOIUrl":"https://doi.org/10.1109/APASIC.2004.1349470","url":null,"abstract":"This paper proposes a new and efficient method for layout migration. In the method, we achieve technology retargeting by optimizing objects and handling hierarchical structure. Circuit elements in the layout are defined as objects. The objects are represented by a set of connected or overlapped rectangles. The object based process in hierarchical structure supports easy handling of circuit elements through the migration process. Experimental results demonstrate the effectiveness of our method on actual layouts. The used layouts in the experiment include simple standard library cells and more complex hierarchical macro blocks composed of standard and custom cells.","PeriodicalId":375715,"journal":{"name":"Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121235570","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 6.25mm/sup 2/ 2.4GHz CMOS 802.11b transceiver 6.25mm/sup 2/ 2.4GHz CMOS 802.11b收发器
Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits Pub Date : 2004-11-01 DOI: 10.1093/ietele/e88-c.8.1716
Yong-Hsiang Hsieh, Wei-Yi Hu, Wen-Kai Li, Shin-Ming Lin, Chao-Liang Chen, David J. Chen, Sao-Jie Chen
{"title":"A 6.25mm/sup 2/ 2.4GHz CMOS 802.11b transceiver","authors":"Yong-Hsiang Hsieh, Wei-Yi Hu, Wen-Kai Li, Shin-Ming Lin, Chao-Liang Chen, David J. Chen, Sao-Jie Chen","doi":"10.1093/ietele/e88-c.8.1716","DOIUrl":"https://doi.org/10.1093/ietele/e88-c.8.1716","url":null,"abstract":"This CMOS transceiver IC exploits the superheterodyne architecture to implement a low-cost RF front-end with only 6.25 mm 2 die area for IEEE 802.11 b standard. The transceiver is implemented in 0.25 μm CMOS process with 2.7 V supply voltage, and achieves a -86 dBm 11 Mb/s receive sensitivity and a 2dBm transmit output power.","PeriodicalId":375715,"journal":{"name":"Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123295868","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
High speed digital smart image sensor with image compression function 具有图像压缩功能的高速数字智能图像传感器
Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits Pub Date : 2004-11-01 DOI: 10.1109/APASIC.2004.1349426
S. Narisawa, K. Masuda, T. Hamamoto
{"title":"High speed digital smart image sensor with image compression function","authors":"S. Narisawa, K. Masuda, T. Hamamoto","doi":"10.1109/APASIC.2004.1349426","DOIUrl":"https://doi.org/10.1109/APASIC.2004.1349426","url":null,"abstract":"We propose a high speed digital smart image sensor on which A/D conversion circuits and digital processing circuits of image compression are integrated. By on-sensor image compression, the proposed sensor can overcome a communication bottle neck between a sensor and peripherals that is one of the most serious problems for achieving high frame rates. The compression method uses the correlation between two consecutive frames. It has some compression modes by controlling spatial and temporal resolutions. In this paper, the algorithm of on-sensor-compression is explained and some experimental results are shown. finally, we show the design of new digital smart sensor.","PeriodicalId":375715,"journal":{"name":"Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits","volume":"24 2","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120890001","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
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