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Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits最新文献

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A dynamically reconfigurable IP for data-intensive applications 用于数据密集型应用程序的动态可重构IP
Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits Pub Date : 2004-11-01 DOI: 10.1109/APASIC.2004.1349512
N. Miyamoto, L. Karnan, K. Kotani, T. Ohmi
{"title":"A dynamically reconfigurable IP for data-intensive applications","authors":"N. Miyamoto, L. Karnan, K. Kotani, T. Ohmi","doi":"10.1109/APASIC.2004.1349512","DOIUrl":"https://doi.org/10.1109/APASIC.2004.1349512","url":null,"abstract":"In this paper, we introduce a report on designing an ASIC which includes a dynamically reconfigurable IP that can change composition within a clock cycle. Empirical design TAT evaluations were made and the results showed that a data-intensive processor equipped with this IP can be designed in 4 weeks.","PeriodicalId":375715,"journal":{"name":"Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122458770","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Fast Fourier transform processor based on low-power and area-efficient algorithm 基于低功耗和面积效率算法的快速傅里叶变换处理器
Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits Pub Date : 2004-11-01 DOI: 10.1109/APASIC.2004.1349448
Jung-Yeol Oh, M. Lim
{"title":"Fast Fourier transform processor based on low-power and area-efficient algorithm","authors":"Jung-Yeol Oh, M. Lim","doi":"10.1109/APASIC.2004.1349448","DOIUrl":"https://doi.org/10.1109/APASIC.2004.1349448","url":null,"abstract":"This paper proposes a new efficient FFT architecture with structured pipeline for OFDM systems, based on radix-2/sup 4/ algorithm. The pipeline architecture with the new algorithm has the same number of multipliers as that of the radix-2/sup 2/ algorithm. However, the multiplier complexity could be reduced by an amount of above 30% by means of replacing a half of programmable multipliers with the newly proposed constant multipliers. A newly proposed complex constant multiplier can enhance the area/power efficiency of the design. From synthesis simulations of a standard 0.35/spl mu/m CMOS process, it achieved above 60% area reduction when compared with the conventional programmable multiplier.","PeriodicalId":375715,"journal":{"name":"Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121098231","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
A simple and fast PC interface for VLSI measurement 一个简单和快速的PC接口的VLSI测量
Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits Pub Date : 2004-11-01 DOI: 10.1109/APASIC.2004.1349510
Y. Mita, M. Takada, T. Shibata
{"title":"A simple and fast PC interface for VLSI measurement","authors":"Y. Mita, M. Takada, T. Shibata","doi":"10.1109/APASIC.2004.1349510","DOIUrl":"https://doi.org/10.1109/APASIC.2004.1349510","url":null,"abstract":"An efficient way to realize VLSI ASIC measurement and demonstration system is connect it to host PC. Interface circuit that manages data transaction to ASIC is necessary. Since designers cannot spend too much time just for interfacing, a straightforward yet performant I/O is needed. In this paper, three examples of in-house interface circuits are presented for ISA, Parallel, and USB.","PeriodicalId":375715,"journal":{"name":"Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117090023","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 1.8V 2.5-5.2 GHz CMOS dual-input two-stage ring VCO 1.8V 2.5-5.2 GHz CMOS双输入两级环形压控振荡器
Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits Pub Date : 2004-11-01 DOI: 10.1109/APASIC.2004.1349429
Wei-Hsuan Tu, J. Yeh, Hung-Chieh Tsai, Chorng-Kuang Wang
{"title":"A 1.8V 2.5-5.2 GHz CMOS dual-input two-stage ring VCO","authors":"Wei-Hsuan Tu, J. Yeh, Hung-Chieh Tsai, Chorng-Kuang Wang","doi":"10.1109/APASIC.2004.1349429","DOIUrl":"https://doi.org/10.1109/APASIC.2004.1349429","url":null,"abstract":"A 1.8V 2.5-to-5.2 GHz dual-input two-stage CMOS voltage-controlled ring oscillator (VCO) is presented. A novel delay cell used for the two-stage ring VCO is proposed to achieve low power dissipation and better phase noise performance. The delay cell adopts both inductive-peaking and shunt-shunt feedback circuit techniques to obtain high gain and wide. Implemented in a 0.18 /spl mu/m CMOS technology using 1.8V supply voltage, the VCO has a wide operating frequency range from 2.5GHz to 5.2GHz with coarse-tune VCO gain of 4.75GHz/V and fine-tune VCO gain of 80MHz/V. At 3.6GHz, the phase noise of the VCO is -90.1dBc/Hz at 1MHz frequency offset with low power consumption of 17mW. Because of the two-stage ring topology, the VCO can provide quadrature outputs. The total chip area is 0.4mm /spl times/ 0.6mm.","PeriodicalId":375715,"journal":{"name":"Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123940690","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 52
An 8-bit 1 Gsps CMOS pipeline ADC 一个8位1 Gsps CMOS流水线ADC
Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits Pub Date : 2004-11-01 DOI: 10.1109/APASIC.2004.1349520
Yun-Jeong Kim, Ja-Hyun Koo, Won-Joo Yun, Shin-Il Lim, Suki Kim
{"title":"An 8-bit 1 Gsps CMOS pipeline ADC","authors":"Yun-Jeong Kim, Ja-Hyun Koo, Won-Joo Yun, Shin-Il Lim, Suki Kim","doi":"10.1109/APASIC.2004.1349520","DOIUrl":"https://doi.org/10.1109/APASIC.2004.1349520","url":null,"abstract":"An 8-bit 1Gsamples/s CMOS pipeline ADC(analog to digital converter) is designed with an open loop circuit design technique. To achieve the 1 GHz sampling rate, an interleaving technique is used. To get low power consumption and small die area, common blocks, such as, a reference string, bias blocks, interpolation amplifiers and pre-amplifiers in comparator are shared. At the 1 GHz sampling rate, simulation results show that the power consumption is 400 mW including digital logic with a power supply of 1.8 V and the SNDR of 45 dB with an input frequency of 207 MHz. The proposed ADC was designed with 0.18 /spl mu/m 6-Metal 1-Poly CMOS process and occupies an die area of 800 /spl mu/m /spl times/ 950 /spl mu/m. The prototype device is now under fabrication.","PeriodicalId":375715,"journal":{"name":"Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126116115","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A design of parallel matched filter with low calculation cost 一种计算成本低的并联匹配滤波器设计
Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits Pub Date : 2004-11-01 DOI: 10.1109/APASIC.2004.1349514
T. Sugawara, Y. Miyanaga
{"title":"A design of parallel matched filter with low calculation cost","authors":"T. Sugawara, Y. Miyanaga","doi":"10.1109/APASIC.2004.1349514","DOIUrl":"https://doi.org/10.1109/APASIC.2004.1349514","url":null,"abstract":"In this report, we propose a new architecture of a matched filter used in CDMA systems. The new architecture reduces the calculation cost of required data correlation significantly. Since the calculation of the correlation into a matched filter becomes quite large amount of operation, the large circuit scale and the high power consumption happen on a mobile system. Accordingly the low calculation cost has been demanded. The proposed matched filter applies two step correlation algorithm into the data processing. Therefore, the amount of the operation can be decreased. In addition, it is expected that the operation speed and the power consumption of a matched filter circuit module are improved.","PeriodicalId":375715,"journal":{"name":"Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits","volume":"102 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132933753","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A quadrilateral-object composer for binary images with reaction-diffusion cellular automata 具有反应扩散元胞自动机的二值图像的四边形对象编写器
Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits Pub Date : 2004-11-01 DOI: 10.1080/17445760500033390
T. Asai, M. Ikebe, Tetsuya Hirose, Y. Amemiya
{"title":"A quadrilateral-object composer for binary images with reaction-diffusion cellular automata","authors":"T. Asai, M. Ikebe, Tetsuya Hirose, Y. Amemiya","doi":"10.1080/17445760500033390","DOIUrl":"https://doi.org/10.1080/17445760500033390","url":null,"abstract":"We will describe a cellular-automaton (CA) LSI that extracts quadrilateral objects, such as box areas filled with the same pixel values, from binary images. We propose an efficient CA algorithm, based on the reaction-diffusion chemical systems model. Each cell in the proposed CA is implemented by a digital circuit called an elemental processor. The CA LSI is constructed by a large number of elemental processors operating in parallel. This parallel operation ensures fast and efficient object extraction when the number of cells (processing pixels) increases. When we assumed a 0.25-/spl mu/m CMOS process with the proposed circuits, the total area of the elemental processor was approximately 5 by 5 /spl mu/m/sup 2/.","PeriodicalId":375715,"journal":{"name":"Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130573617","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A digitized LVDS driver with simultaneous switching noise rejection 同时抑制开关噪声的数字化LVDS驱动器
Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits Pub Date : 2004-11-01 DOI: 10.1109/APASIC.2004.1349460
Hsin-Wen Wang, Hungwen Lu, Chau-chin Su
{"title":"A digitized LVDS driver with simultaneous switching noise rejection","authors":"Hsin-Wen Wang, Hungwen Lu, Chau-chin Su","doi":"10.1109/APASIC.2004.1349460","DOIUrl":"https://doi.org/10.1109/APASIC.2004.1349460","url":null,"abstract":"In this paper, a Digitized LVDS Driver with SSN (Simultaneous switching noise) rejection is proposed, which is fabricated by TSMC 0.18/spl mu/m CMOS technology. First, the power consumption and chip area are greatly decreased due to the design of digitized driver but we suffered the SSN noise. Second, the method which modifies the driver's control signal greatly reduces the ground bounce, and simultaneously solved the ground bound problem mentioned above. Third, the driver can calibrate the output differential mode by the control signal outside the chip by way of the controllable driver. According to the simulation results, ground bounce reduced from 175mV to 95mV, 55% diminished, and the measurement output jitter (pk-pk) is less than 48ps @1.25Gbps. The driver area is only 210/spl mu/m /spl times/ 210/spl mu/m and power consumption is less than 19mW, which are extremely lower then the conventional LVDS Driver. The proposed programmable driver can also be applied to the 1.5Gbps Serial ATA standard or 2.5Gbps PCI-Express.","PeriodicalId":375715,"journal":{"name":"Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130315776","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Reconfigurable RF circuit design for multi-band wireless chip 多波段无线芯片可重构射频电路设计
Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits Pub Date : 2004-11-01 DOI: 10.1109/APASIC.2004.1349518
Y. Yoshihara, H. Sugawara, H. Ito, K. Okada, K. Masu
{"title":"Reconfigurable RF circuit design for multi-band wireless chip","authors":"Y. Yoshihara, H. Sugawara, H. Ito, K. Okada, K. Masu","doi":"10.1109/APASIC.2004.1349518","DOIUrl":"https://doi.org/10.1109/APASIC.2004.1349518","url":null,"abstract":"This paper presents a reconfigurable RF circuit architecture for Multi-band Wireless Chip. The circuit can be reconstructed and tuned to various applications and the best configuration by itself. Multi-band VCO using an on-chip variable inductor achieves tuning range of 37.8%, which is one of the key circuits of reconfigurable RF circuit.","PeriodicalId":375715,"journal":{"name":"Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133608763","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
False aggressors pruning using path sensitization and logic implications 使用路径敏化和逻辑暗示的假攻击者修剪
Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits Pub Date : 2004-11-01 DOI: 10.1109/APASIC.2004.1349471
Hyungwoo Lee, Juho Kim
{"title":"False aggressors pruning using path sensitization and logic implications","authors":"Hyungwoo Lee, Juho Kim","doi":"10.1109/APASIC.2004.1349471","DOIUrl":"https://doi.org/10.1109/APASIC.2004.1349471","url":null,"abstract":"Coupled line switching can contribute to a large portion of the delay as well as the functionality of a circuit. In order to fix a crosstalk noise in noise analysis, it is necessary an additional design cost. Therefore, aggressor nodes that cannot affect victim node have to pruning. In this paper, we present an efficient false aggressor pruning algorithm with functional correlation. Path sensitization algorithm and logic implication approach that use functional information to identify false coupling interaction between coupled lines. Our experimental results show an average of 5.4% aggressor pruning and 14.6% delay reduction due to pruning.","PeriodicalId":375715,"journal":{"name":"Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134564755","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
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