Design and implementation of word-parallel digital associative memories

Abstract

We present word-parallel digital associative memories with exact Hamming/Manhattan distance computation. A logic-in-memory digital implementation achieves the word-parallel and hierarchical search architecture. It attains a high-speed operation with a large input number, and detects the data close to the input with a fewer number of clocks. The circuit implementation allows unlimited data capacity and achieves a low-voltage operation under 1.0 V for system-on-a-chip applications. The capacity scalability makes it easy to compute a function of Manhattan distance evaluation using thermometer encoding. We have designed 64-bit 32-word associative memories using a 1P5M 0.18 /spl mu/m CMOS process. It achieves 411.5 MHz and 40.0 MHz operations at a supply voltage of 1.8 V and 0.75 V, respectively.